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authorDuncan Laurie <dlaurie@chromium.org>2013-07-22 15:33:10 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 07:39:00 +0100
commit8d716b98d0b0498123f7afc68188f60c9f0c0b6b (patch)
tree9bbfd24f2e52ad06d8844fb2bdb4200327a16075 /src/mainboard/google/falco
parent8056dc657410ee2b82e136548f9ebd00ba98fe30 (diff)
downloadcoreboot-8d716b98d0b0498123f7afc68188f60c9f0c0b6b.tar.xz
slippy/falco/peppy: update ACPI C-state settings
Since these boards do not support C10 we should not bother advertising that state in the ACPI _CST. Instead use this map: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62898 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/falco')
-rw-r--r--src/mainboard/google/falco/devicetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index f5a40e15a3..b490d12a41 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -30,12 +30,12 @@ chip northbridge/intel/haswell
device lapic 0xACAC off end
register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S)
- register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S)
- register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
end
end