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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-19 09:46:33 -0600
committerPatrick Georgi <pgeorgi@google.com>2016-09-20 21:54:45 +0200
commit531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (patch)
tree0beaa7220a61927e2bc0a4d59eb1827b73fe6c02 /src/mainboard/google/falco
parent04f8fd981fd49e9929fea2b27991e78673fc57a3 (diff)
downloadcoreboot-531b87ac4e8038aedf9c44c29fe2c1fc31adb346.tar.xz
src/mainboard/getac - kontron: Add space around operators
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/falco')
-rw-r--r--src/mainboard/google/falco/gma.c2
-rw-r--r--src/mainboard/google/falco/i915io.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c
index 986d9c393e..c76c50ea9b 100644
--- a/src/mainboard/google/falco/gma.c
+++ b/src/mainboard/google/falco/gma.c
@@ -90,7 +90,7 @@ static void palette(void)
unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){
- gtt_write(_LGC_PALETTE_A + (i<<2),color);
+ gtt_write(_LGC_PALETTE_A + (i << 2),color);
}
}
diff --git a/src/mainboard/google/falco/i915io.c b/src/mainboard/google/falco/i915io.c
index 0936de9031..5f33586d36 100644
--- a/src/mainboard/google/falco/i915io.c
+++ b/src/mainboard/google/falco/i915io.c
@@ -84,8 +84,8 @@ void runio(struct intel_dp *dp)
gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
- gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
- gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
+ gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x0001000a);
+ gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x07d0000a);
intel_dp_set_bw(dp);
intel_dp_set_lane_count(dp);