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| author | Shelley Chen <shchen@chromium.org> | 2017-06-29 14:58:59 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-14 22:47:31 +0000 |
| commit | 8c81c6ac436c8eac0e312cd2a34133d4a7f5d991 (patch) | |
| tree | 3ee4dd4afce1ececfb6db0902dbdd6f13e5c4c94 /src/mainboard/google/fizz/devicetree.cb | |
| parent | 20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1 (diff) | |
| download | coreboot-8c81c6ac436c8eac0e312cd2a34133d4a7f5d991.tar.xz | |
google/fizz: Override PL2 and SysPL2 values
Set PL2 and SysPL2 for Fizz based on cpu id.
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a493de5535..bf9f0c9ef9 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -210,7 +210,7 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "tdp_pl2_override" = "7" + register "tdp_psyspl2" = "90" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration |