diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-11-22 17:31:40 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2017-11-25 08:31:55 +0000 |
| commit | eca98ba46051d5e2091ac4ad29b053321f06ff73 (patch) | |
| tree | 0865f2f9b7d8aa40051221c2a38b5ff851ec766d /src/mainboard/google/fizz/gpio.h | |
| parent | 5537f02bd59dd064ace6e06e3de473140550c9ab (diff) | |
| download | coreboot-eca98ba46051d5e2091ac4ad29b053321f06ff73.tar.xz | |
google/fizz: Remove tpm i2c configs from Kconfig
We are disabling tpm over i2c, so the configs are not needed
anymore.
BUG=b:65056998
BRANCH=None
TEST=emerge fizz and make sure can still boot up.
Change-Id: Id88f32fa952801749544534442fc15d85fc1a892
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/gpio.h')
| -rw-r--r-- | src/mainboard/google/fizz/gpio.h | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index d54a1fed0f..e6dc3a751b 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -92,7 +92,6 @@ static const struct pad_config gpio_table[] = { /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, @@ -101,12 +100,6 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -#else -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -#endif /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ /* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */ @@ -142,15 +135,8 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SDA */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SCL */ -#else /* I2C1_SDA */ PAD_CFG_NC(GPP_C18), /* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -#endif /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ @@ -275,7 +261,6 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -#if IS_ENABLED(CONFIG_FIZZ_USE_SPI_TPM) /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, @@ -284,13 +269,6 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -#endif -#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SDA */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, - NF1), /* PCH_I2C1_H1_3V3_SCL */ -#endif /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ |