diff options
author | Shelley Chen <shchen@chromium.org> | 2017-03-15 15:25:48 -0700 |
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committer | Martin Roth <martinroth@google.com> | 2017-03-23 19:58:24 +0100 |
commit | 243dc3913df4bc112e074931c7726a6eb21273c6 (patch) | |
tree | 74aaec53555eee5502cfcf253a3ebc6f79cfe375 /src/mainboard/google/fizz/romstage.c | |
parent | 7de031759b916bbb91e74e6eea371b5ca87e6bd5 (diff) | |
download | coreboot-243dc3913df4bc112e074931c7726a6eb21273c6.tar.xz |
google/fizz: Add new board
Creating google/fizz directory based on poppy (using kabylake and FSP
2.0). Only making name changes and Copyright year changes. Many
poppy-specific configs left in and will be updated in follup CLs.
BUG=b:35775024
BRANCH=None
TEST=Compile fizz board
Change-Id: Icab3639a53fef65e904e797028916fda879fff7c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/18796
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/romstage.c')
-rw-r--r-- | src/mainboard/google/fizz/romstage.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c new file mode 100644 index 0000000000..34aaad0b9f --- /dev/null +++ b/src/mainboard/google/fizz/romstage.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> + +#include <fsp/soc_binding.h> + +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0xCC, 0x33, 0x00, 0x33, 0xCC, 0x33, + 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 } + }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 2, 3, 1, 0, 4, 7, 6, 5 }, + { 5, 6, 0, 3, 4, 7, 2, 1 }, + }; + /* Rcomp resistor */ + const u16 rcomp_resistor[] = { 200, 81, 162 }; + /* Rcomp target */ + const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + + memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); + memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; +} |