diff options
| author | Kane Chen <kane.chen@intel.com> | 2017-11-14 11:38:01 +0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2017-11-27 03:55:42 +0000 |
| commit | 73031bcce071f6e760cc0655200dd3be2f39c8b7 (patch) | |
| tree | ada50f4d931400d333fb9ee6f6608b0d9786d5f6 /src/mainboard/google/fizz/romstage.c | |
| parent | 6919a9376e1fefc1072b638d754588d8ba287aed (diff) | |
| download | coreboot-73031bcce071f6e760cc0655200dd3be2f39c8b7.tar.xz | |
google/fizz: correct memory rcomp settings
Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz
TEST= boot ok and the system can enter and resume from S3.
Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz/romstage.c')
| -rw-r--r-- | src/mainboard/google/fizz/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 405c4c18b4..335662ef6d 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -24,9 +24,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; /* Rcomp resistor */ - const u16 rcomp_resistor[] = { 200, 81, 162 }; + const u16 rcomp_resistor[] = { 121, 81, 100 }; /* Rcomp target */ - const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; + const u16 rcomp_target[] = { 100, 40, 20, 20, 26 }; /* SPD was saved in S0/S5 path, skips it when resumes from S3 */ if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME) |