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author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-10 01:24:11 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:13:23 +0000 |
commit | 97c5464443306f26b61cec3a0f50108a5c06b7ef (patch) | |
tree | f085457907ad200a0d9d9be8a07c937e755fae91 /src/mainboard/google/fizz/variants/baseboard | |
parent | 19c2ce7639d55908d210782ae5a0315396cc7eaf (diff) | |
download | coreboot-97c5464443306f26b61cec3a0f50108a5c06b7ef.tar.xz |
skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/fizz/variants/baseboard')
-rw-r--r-- | src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index f02accec71..b8455fe9e9 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -325,8 +325,10 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "tdp_psyspl2" = "90" - register "psys_pmax" = "120" + register "power_limits_config" = "{ + .tdp_psyspl2 = 90, + .psys_pmax = 120, + }" register "tcc_offset" = "6" # TCC of 94C device cpu_cluster 0 on |