diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-04-07 09:15:42 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-24 19:17:47 +0200 |
| commit | 031c81863316e32ddec2a8360011e424fe9c845c (patch) | |
| tree | bf35d2e840a31e4de602f22b4027ead7ce4353db /src/mainboard/google/fizz | |
| parent | b7f28700f4e114a12215842d31e29af734a191e2 (diff) | |
| download | coreboot-031c81863316e32ddec2a8360011e424fe9c845c.tar.xz | |
google/fizz: Configure memory
Read DRAM SPD and populate MemorySpdPtr fields
in UPD data structure for FSP.
BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
We are currently working on bringup and have no
hardware to test on yet.
Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/fizz')
| -rw-r--r-- | src/mainboard/google/fizz/Kconfig | 9 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/romstage.c | 11 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 377a13c773..2d2e6b78c0 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 select SOC_INTEL_KABYLAKE + select GENERIC_SPD_BIN config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -38,4 +39,12 @@ config MAINBOARD_FAMILY config MAX_CPUS int default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 endif diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 8bcfcd3d44..be1d552156 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -15,6 +15,7 @@ #include <soc/romstage.h> #include <string.h> +#include <spd_bin.h> #include <fsp/soc_binding.h> @@ -28,4 +29,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + /* Read spd block to get memory config */ + struct spd_block blk; + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + + dump_spd_info(&blk); } |