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authorEmil Lundmark <lndmrk@chromium.org>2018-05-22 19:32:35 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-01 08:16:00 +0000
commit2ad7ea07b82f99ce9ff751774143e6ebbf02090c (patch)
tree1d41c617875bc61eb940c0180d45500eaa233822 /src/mainboard/google/fizz
parent9022b9d2aaa2421a069c26ac656b3954138a0674 (diff)
downloadcoreboot-2ad7ea07b82f99ce9ff751774143e6ebbf02090c.tar.xz
mb/google/fizz: Add USB port info
This adds all USB ports to the device tree. Additionally, it adds _PS0 and _PS3 ACPI methods for the visible USB A ports, which makes it possible to control the port power (VBUS) of each port individually. Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/fizz')
-rw-r--r--src/mainboard/google/fizz/Kconfig2
-rw-r--r--src/mainboard/google/fizz/acpi/usb.asl125
-rw-r--r--src/mainboard/google/fizz/devicetree.cb74
-rw-r--r--src/mainboard/google/fizz/dsdt.asl3
4 files changed, 203 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 1ca3090048..19385fff81 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -5,7 +5,9 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select DRIVERS_SPI_ACPI
+ select DRIVERS_USB_ACPI
select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl
new file mode 100644
index 0000000000..f769a20317
--- /dev/null
+++ b/src/mainboard/google/fizz/acpi/usb.asl
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.XHCI.RHUB.HS02)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (2)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (2)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS03)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (3)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (3)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS04)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (4)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (4)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS05)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (0)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (0)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS06)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (1)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (1)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS02)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (2)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (2)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS03)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (3)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (3)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS04)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (4)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (4)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS05)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (0)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (0)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS06)
+{
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (1)
+ }
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (1)
+ }
+}
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index db46bf8c90..45b2736b1a 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -326,7 +326,79 @@ chip soc/intel/skylake
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
- device pci 14.0 on end # USB xHCI
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Rear""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Left""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Front Right""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Front Left""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Right""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Middle""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Rear""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Left""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Front Right""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Front Left""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Right""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Middle""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.5 on end
+ end
+ end
+ end
+ end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 15.0 on end # I2C #0
diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl
index 24abfc17af..69d915805c 100644
--- a/src/mainboard/google/fizz/dsdt.asl
+++ b/src/mainboard/google/fizz/dsdt.asl
@@ -67,4 +67,7 @@ DefinitionBlock(
/* Dynamic Platform Thermal Framework */
#include "acpi/dptf.asl"
}
+
+ /* USB port entries */
+ #include "acpi/usb.asl"
}