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authorShelley Chen <shchen@chromium.org>2017-11-17 17:14:19 -0800
committerShelley Chen <shchen@google.com>2017-11-20 23:33:00 +0000
commit9af3f2d63a92d50edf60cfdc69b788ea0e7e4951 (patch)
treec79409a730befb762fee3496e83213962e54275a /src/mainboard/google/fizz
parent75b154334d0e1273a4164fea87730c28d47109a5 (diff)
downloadcoreboot-9af3f2d63a92d50edf60cfdc69b788ea0e7e4951.tar.xz
mainboard/google/fizz: Enable separate MRC cache for recovery mode
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:69473883 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/fizz')
-rw-r--r--src/mainboard/google/fizz/Kconfig2
-rw-r--r--src/mainboard/google/fizz/chromeos.fmd31
2 files changed, 20 insertions, 13 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 64748243fa..b1f353d53d 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -26,6 +26,8 @@ config VBOOT
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select VBOOT_EC_EFS
select VBOOT_PHYSICAL_REC_SWITCH
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config DRIVER_TPM_I2C_BUS
depends on FIZZ_USE_I2C_TPM
diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd
index 58b612781f..bdadcf728d 100644
--- a/src/mainboard/google/fizz/chromeos.fmd
+++ b/src/mainboard/google/fizz/chromeos.fmd
@@ -4,24 +4,29 @@ FLASH@0xff000000 0x1000000 {
SI_ME@0x1000 0x1ff000
}
SI_BIOS@0x200000 0xe00000 {
- RW_SECTION_A@0x0 0x3f0000 {
+ RW_SECTION_A@0x0 0x3e8000 {
VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x3dffc0
- RW_FWID_A@0x3effc0 0x40
+ FW_MAIN_A(CBFS)@0x10000 0x3d7fc0
+ RW_FWID_A@0x3e7fc0 0x40
}
- RW_SECTION_B@0x3f0000 0x3f0000 {
+ RW_SECTION_B@0x3e8000 0x3e8000 {
VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x3dffc0
- RW_FWID_B@0x3effc0 0x40
+ FW_MAIN_B(CBFS)@0x10000 0x3d7fc0
+ RW_FWID_B@0x3e7fc0 0x40
}
- RW_MRC_CACHE@0x7e0000 0x10000
- RW_ELOG@0x7f0000 0x4000
- RW_SHARED@0x7f4000 0x4000 {
- SHARED_DATA@0x0 0x2000
- VBLOCK_DEV@0x2000 0x2000
+ RW_MISC@0x7d0000 0x30000 {
+ UNIFIED_MRC_CACHE@0x0 0x20000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ }
+ RW_ELOG@0x20000 0x4000
+ RW_SHARED@0x24000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x28000 0x2000
+ RW_NVRAM@0x2a000 0x6000
}
- RW_VPD@0x7f8000 0x2000
- RW_NVRAM@0x7fa000 0x6000
RW_LEGACY(CBFS)@0x800000 0x200000
WP_RO@0xa00000 0x400000 {
RO_VPD@0x0 0x4000