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authorShelley Chen <shchen@chromium.org>2017-09-28 10:26:26 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-20 22:49:42 +0000
commitbdfc5f5790ce632b287411c915ea163e0d4e84e1 (patch)
tree01c511b1ba2138b0cb55819accde1c9b7402bbe6 /src/mainboard/google/fizz
parentebd533065f0dd7f00d6452e5019f685b769d5b0e (diff)
downloadcoreboot-bdfc5f5790ce632b287411c915ea163e0d4e84e1.tar.xz
google/fizz: Set PL2 value based on sku id/charge max power
Set PL2 based on either 90% of usb c charger's max power or sku id if using a barrel jack. BUG=b:37473486 BRANCH=None TEST=output debug info for different skus and make sure PL2 set correctly. Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/fizz')
-rw-r--r--src/mainboard/google/fizz/gpio.h6
-rw-r--r--src/mainboard/google/fizz/mainboard.c54
2 files changed, 46 insertions, 14 deletions
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index dfd206dd26..d063e8d9d8 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -31,6 +31,12 @@
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
+/* SKU_ID GPIOs */
+#define GPIO_SKU_ID0 GPP_C12
+#define GPIO_SKU_ID1 GPP_C13
+#define GPIO_SKU_ID2 GPP_C14
+#define GPIO_SKU_ID3 GPP_C15
+
#ifndef __ACPI__
/* Pad configuration in ramstage */
/* Leave eSPI pins untouched from default settings */
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index 76fb2b8f9b..ae3767579e 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -18,34 +18,60 @@
#include <chip.h>
#include <device/device.h>
#include <ec/ec.h>
-#include <intelblocks/mp_init.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <mainboard/google/fizz/gpio.h>
+#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#define FIZZ_SKU_ID_I7_U42 0x4
+#define FIZZ_PL2_I7_U42 44
+#define FIZZ_PL2_OTHERS 29
+/*
+ * For type-C chargers, set PL2 to 90% of max power to account for
+ * cable loss and FET Rdson loss in the path from the source.
+ */
+#define GET_TYPEC_PL2(w) (9 * (w) / 10)
+
static const char *oem_id = "GOOGLE";
static const char *oem_table_id = "FIZZ";
/*
* mainboard_get_pl2
*
- * @return value Pl2 should be set to based on cpu id
+ * @return value Pl2 should be set to
*
- * TODO: This is purely based on cpu id, which only works for the
- * current build because we have a different cpu id per sku. However,
- * on the next build, we'll have distinct board ids per sku. We'll
- * need to modify that at this point.
+ * Check if charger is USB C. If so, set to 90% of the max value.
+ * Otherwise, set PL2 based on sku id.
*/
static u32 mainboard_get_pl2(void)
{
- struct cpuid_result cpuidr;
-
- cpuidr = cpuid(1);
- if (cpuidr.eax == CPUID_KABYLAKE_Y0) {
- /* i7 needs higher pl2 */
- return 44;
- }
- return 29;
+ const gpio_t sku_id_gpios[] = {
+ GPIO_SKU_ID0,
+ GPIO_SKU_ID1,
+ GPIO_SKU_ID2,
+ GPIO_SKU_ID3,
+ };
+ enum usb_chg_type type;
+ u32 watts;
+
+ int rv = google_chromeec_get_usb_pd_power_info(&type, &watts);
+ int sku_id;
+
+ /* If we can't get charger info or not PD charger, assume barrel jack */
+ if (rv != 0 || type != USB_CHG_TYPE_PD) {
+ /* using the barrel jack, get PL2 based on sku id */
+ watts = FIZZ_PL2_OTHERS;
+ sku_id = gpio_base2_value(sku_id_gpios,
+ ARRAY_SIZE(sku_id_gpios));
+ if (sku_id == FIZZ_SKU_ID_I7_U42)
+ watts = FIZZ_PL2_I7_U42;
+ } else
+ watts = GET_TYPEC_PL2(watts);
+
+ return watts;
}
static void mainboard_init(device_t dev)