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authorLijian Zhao <lijian.zhao@intel.com>2019-01-11 07:54:48 -0800
committerNico Huber <nico.h@gmx.de>2019-01-11 18:59:21 +0000
commit64925b5128d8ed27bd1780f6cb25805aecc659e6 (patch)
tree1f82ad27170650310126751cab059b649d07d3c4 /src/mainboard/google/fizz
parentdd217362d44f197b08fa69f3c2c14e743e1bc90b (diff)
downloadcoreboot-64925b5128d8ed27bd1780f6cb25805aecc659e6.tar.xz
soc/mainboard: Update mainboard UART Kconfig
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/google/fizz')
-rw-r--r--src/mainboard/google/fizz/Kconfig4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 26f6f3af3d..1748d894e5 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
+ select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
@@ -97,4 +98,7 @@ config INCLUDE_NHLT_BLOBS_KARMA
select NHLT_DMIC_4CH
select NHLT_MAX98357
+config UART_FOR_CONSOLE
+ int
+ default 2
endif # BOARD_GOOGLE_BASEBOARD_FIZZ