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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-06-11 01:19:45 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-11 08:51:18 +0000 |
| commit | f061a73ab9654ccae73b2fcbd58d8f08017bae59 (patch) | |
| tree | 629e12ba43095f226b3e8fa6d6951cf8fd5f6a95 /src/mainboard/google/fizz | |
| parent | 3b7668325b6a891d2382c360cf41e64f662256c9 (diff) | |
| download | coreboot-f061a73ab9654ccae73b2fcbd58d8f08017bae59.tar.xz | |
google/fizz: fix LAN driver chip_info attachment
As a result of commit:
[711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device
fizz's chip_info for the LAN driver is being overwritten/nulled, as the
LAN device is on function 2 (PCIe port 3), but the driver info was set
for the post-swapped PCIe port (1).
Move the driver chip_info to function 2/port 3, so that it follows the
PCI device function when swapped after FSP-s, and is correctly passed
to the LAN driver.
Test: boot google/fizz (teemo variant), check cbmem console and
verify ethernet MAC address and LED config correctly set.
Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/fizz')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 67828d1ffd..0ac403efa5 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -429,17 +429,17 @@ chip soc/intel/skylake end end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP + device pci 1c.2 on chip drivers/net register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" register "device_index" = "1" device pci 00.0 on end end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - # PCI Express Port 3 for LAN, but will be swapped to port 1 - device pci 1c.2 on end + end # PCI Express Port 3 device pci 1c.3 on chip drivers/intel/wifi register "wake" = "GPE0_PCI_EXP" |