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authorPatrick Georgi <pgeorgi@chromium.org>2015-06-22 19:43:18 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-06-30 21:47:12 +0200
commitfd49d6faf98eb45006a20869da798558cea9606e (patch)
tree45c375eefbac9a402dba32d1ee8403d670c93df2 /src/mainboard/google/foster
parentb12a448c9709a4d78410ac4e79a72f28096871ce (diff)
downloadcoreboot-fd49d6faf98eb45006a20869da798558cea9606e.tar.xz
google/foster: add new mainboard
This is an nvidia t210 based board. This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I8630e86a4b0e8756693f8989ce147d6d762cefe1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10634 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/foster')
-rw-r--r--src/mainboard/google/foster/Kconfig97
-rw-r--r--src/mainboard/google/foster/Kconfig.name3
-rw-r--r--src/mainboard/google/foster/Makefile.inc50
-rw-r--r--src/mainboard/google/foster/bct/Makefile.inc30
-rw-r--r--src/mainboard/google/foster/bct/cfg2inc.sh34
-rw-r--r--src/mainboard/google/foster/bct/emmc.cfg16
-rw-r--r--src/mainboard/google/foster/bct/jtag.cfg16
-rw-r--r--src/mainboard/google/foster/bct/odmdata.cfg1
-rw-r--r--src/mainboard/google/foster/bct/sdram-samsung-3GB-204.cfg691
-rw-r--r--src/mainboard/google/foster/bct/sdram-samsung-3GB-204.inc477
-rw-r--r--src/mainboard/google/foster/bct/sdram-unused.inc4
-rw-r--r--src/mainboard/google/foster/bct/spi.cfg16
-rw-r--r--src/mainboard/google/foster/boardid.c28
-rw-r--r--src/mainboard/google/foster/bootblock.c95
-rw-r--r--src/mainboard/google/foster/chromeos.c102
-rw-r--r--src/mainboard/google/foster/devicetree.cb95
-rw-r--r--src/mainboard/google/foster/ec_dummy.c9
-rw-r--r--src/mainboard/google/foster/mainboard.c129
-rw-r--r--src/mainboard/google/foster/memlayout.ld6
-rw-r--r--src/mainboard/google/foster/pmic.c93
-rw-r--r--src/mainboard/google/foster/pmic.h74
-rw-r--r--src/mainboard/google/foster/reset.c29
-rw-r--r--src/mainboard/google/foster/romstage.c40
-rw-r--r--src/mainboard/google/foster/verstage.c29
24 files changed, 2164 insertions, 0 deletions
diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig
new file mode 100644
index 0000000000..571a3b196e
--- /dev/null
+++ b/src/mainboard/google/foster/Kconfig
@@ -0,0 +1,97 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+if BOARD_GOOGLE_FOSTER
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ID_AUTO
+ select BOARD_ROMSIZE_KB_4096
+ select CHROMEOS_VBNV_FLASH
+ select SPI_FLASH
+ select SOC_NVIDIA_TEGRA210
+ select MAINBOARD_HAS_BOOTBLOCK_INIT
+ select MAINBOARD_HAS_CHROMEOS
+ select VIRTUAL_DEV_SWITCH
+ select BOOTROM_SDRAM_INIT # use BootRom to config sdram
+ select COMMON_CBFS_SPI_WRAPPER
+ select SPI_FLASH_WINBOND
+
+config MAINBOARD_DIR
+ string
+ default google/foster
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Foster"
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+choice
+ prompt "BCT boot media"
+ default FOSTER_BCT_CFG_SPI
+ help
+ Which boot media to configure the BCT for.
+
+config FOSTER_BCT_CFG_SPI
+ bool "SPI"
+ help
+ Configure the BCT for booting from SPI.
+
+config FOSTER_BCT_CFG_EMMC
+ bool "eMMC"
+ help
+ Configure the BCT for booting from eMMC.
+
+endchoice
+
+config BOOT_MEDIA_SPI_BUS
+ int "SPI bus with boot media ROM"
+ range 1 7
+ depends on FOSTER_BCT_CFG_SPI
+ default 7
+ help
+ Which SPI bus the boot media is connected to.
+
+config BOOT_MEDIA_SPI_CHIP_SELECT
+ int "Chip select for SPI boot media"
+ range 0 3
+ depends on FOSTER_BCT_CFG_SPI
+ default 0
+ help
+ Which chip select to use for boot media.
+
+# For foster, we are using vboot2. Thus, index for stages:
+# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
+# VBOOT_RAMSTAGE_INDEX -> Use 0x3
+config VBOOT_RAMSTAGE_INDEX
+ hex
+ default 0x3
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x2
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x20
+
+endif # BOARD_GOOGLE_FOSTER
diff --git a/src/mainboard/google/foster/Kconfig.name b/src/mainboard/google/foster/Kconfig.name
new file mode 100644
index 0000000000..b7e6f37ae4
--- /dev/null
+++ b/src/mainboard/google/foster/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_GOOGLE_FOSTER
+ bool "Foster"
+
diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc
new file mode 100644
index 0000000000..29478c0649
--- /dev/null
+++ b/src/mainboard/google/foster/Makefile.inc
@@ -0,0 +1,50 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+## Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# Add a handler for BCT config files
+$(call add-special-class,bct-cfg)
+bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
+
+$(obj)/generated/bct.cfg:
+ @printf " CAT $(subst $(obj)/,,$(@))\n"
+ cat $^ > $@
+
+subdirs-y += bct
+
+bootblock-y += bootblock.c
+bootblock-y += pmic.c
+bootblock-y += reset.c
+
+verstage-y += verstage.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
+romstage-y += reset.c
+romstage-y += romstage.c
+romstage-y += chromeos.c
+
+ramstage-y += boardid.c
+ramstage-y += mainboard.c
+ramstage-y += reset.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
+verstage-y += memlayout.ld
diff --git a/src/mainboard/google/foster/bct/Makefile.inc b/src/mainboard/google/foster/bct/Makefile.inc
new file mode 100644
index 0000000000..88fed7edb2
--- /dev/null
+++ b/src/mainboard/google/foster/bct/Makefile.inc
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2013 Google Inc.
+## Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+bct-cfg-$(CONFIG_FOSTER_BCT_CFG_EMMC) += emmc.cfg
+bct-cfg-$(CONFIG_FOSTER_BCT_CFG_SPI) += spi.cfg
+bct-cfg-y += odmdata.cfg
+bct-cfg-y += jtag.cfg
+#NOTE: When full LPDDR4 SDRAM config is done in romstage, remove this
+bct-cfg-$(CONFIG_BOOTROM_SDRAM_INIT) += sdram-samsung-3GB-204.cfg
+
+# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
+# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
+# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage.
diff --git a/src/mainboard/google/foster/bct/cfg2inc.sh b/src/mainboard/google/foster/bct/cfg2inc.sh
new file mode 100644
index 0000000000..f8f3c441c4
--- /dev/null
+++ b/src/mainboard/google/foster/bct/cfg2inc.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2014 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+
+bct_cfg2inc() {
+ local in_file="$1"
+ local out_file="$2"
+ echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}"
+ # Note currently we can only handle DDR3 type memory, even in C
+ # implementation.
+ sed "/^#.*$/d; s/^SDRAM.0./ /; s/\r$//; s/;$/,/;" \
+ "${in_file}" >> "${out_file}"
+ echo "}," >>"${out_file}"
+}
+
+for file in $@; do
+ echo "Generating $file => ${file%cfg}inc..."
+ bct_cfg2inc "${file}" "${file%cfg}inc"
+done
diff --git a/src/mainboard/google/foster/bct/emmc.cfg b/src/mainboard/google/foster/bct/emmc.cfg
new file mode 100644
index 0000000000..4b6b5d5672
--- /dev/null
+++ b/src/mainboard/google/foster/bct/emmc.cfg
@@ -0,0 +1,16 @@
+# Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00210001;
+BlockSize = 0x00004000;
+PageSize = 0x00000200;
+PartitionSize = 0x01000000;
+
+#
+# T210 bct only supports one boot device
+#
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;
diff --git a/src/mainboard/google/foster/bct/jtag.cfg b/src/mainboard/google/foster/bct/jtag.cfg
new file mode 100644
index 0000000000..e9bbd024a5
--- /dev/null
+++ b/src/mainboard/google/foster/bct/jtag.cfg
@@ -0,0 +1,16 @@
+#
+# Set DebugCtrl to 1 to reenable Jtag
+#
+DebugCtrl = 0;
+#
+# Fill in chip unique id
+#
+# ChipUid can be found by running tegrarcm in tegra recovery mode
+# (also hooking up A-A USB cable) and looking for console output
+# on line starting with "Chip UID:"
+#
+# Command example:
+# $ sudo tegrarcm --bct=/build/foster/firmware/bct/board.bct --bootloader=/build/foster/firmware/u-boot.bin --loadaddr=0x80108000
+# Where board.bct and u-boot.bin do not have to be prebuilt.
+#
+ChipUid = 0x00000000000000000000000000000000;
diff --git a/src/mainboard/google/foster/bct/odmdata.cfg b/src/mainboard/google/foster/bct/odmdata.cfg
new file mode 100644
index 0000000000..45648af315
--- /dev/null
+++ b/src/mainboard/google/foster/bct/odmdata.cfg
@@ -0,0 +1 @@
+OdmData = 0x00294000;
diff --git a/src/mainboard/google/foster/bct/sdram-samsung-3GB-204.cfg b/src/mainboard/google/foster/bct/sdram-samsung-3GB-204.cfg
new file mode 100644
index 0000000000..d12f6b90b8
--- /dev/null
+++ b/src/mainboard/google/foster/bct/sdram-samsung-3GB-204.cfg
@@ -0,0 +1,691 @@
+# CFG Version 06
+# Do not edit. Generated by t210_emc_reg_tool_P972.exe V9.7.2. Command:
+# t210_emc_reg_tool_P972.exe -i E2581_3GB.par 04.90196078431372549019 -dram_board_cfg 33
+# -data_bus_to_0 1 -fly_by_time_ps 1700 -dbi_rd_en 1 -is_bkv 1 -t T210_DSC_E2581A00_lpddr4_tbkv_est_072514.txt
+# -o E2581_A00_3GB_P972_configs\E2581_A00_3GB_Samsung_4GB_lpddr4_204Mhz_P972_v1.cfg
+# Parameter file: E2581_3GB.par, tck = 4.90 ns (204.00 MHz)
+SDRAM[0].MemoryType = NvBootMemoryType_LpDdr4;
+SDRAM[0].PllMInputDivider = 0x00000001;
+SDRAM[0].PllMFeedbackDivider = 0x00000022;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].PllMSetupControl = 0x00000000;
+SDRAM[0].PllMPostDivider = 0x00000000;
+SDRAM[0].PllMKCP = 0x00000000;
+SDRAM[0].PllMKVCO = 0x00000000;
+SDRAM[0].EmcBctSpare0 = 0x00000000;
+SDRAM[0].EmcBctSpare1 = 0x00000000;
+SDRAM[0].EmcBctSpare2 = 0x00000000;
+SDRAM[0].EmcBctSpare3 = 0x00000000;
+SDRAM[0].EmcBctSpare4 = 0x7001bc3c;
+SDRAM[0].EmcBctSpare5 = 0x00000032;
+SDRAM[0].EmcBctSpare6 = 0x7001b404;
+SDRAM[0].EmcBctSpare7 = 0x71245603;
+SDRAM[0].EmcBctSpare8 = 0x7000e6c8;
+SDRAM[0].EmcBctSpare9 = 0x00000000;
+SDRAM[0].EmcBctSpare10 = 0x00000000;
+SDRAM[0].EmcBctSpare11 = 0x00000000;
+SDRAM[0].EmcBctSpare12 = 0x7001bc3c;
+SDRAM[0].EmcBctSpare13 = 0x00000033;
+SDRAM[0].EmcClockSource = 0x40188002;
+SDRAM[0].EmcClockSourceDll = 0x40000000;
+SDRAM[0].ClkRstControllerPllmMisc2Override = 0x00000000;
+SDRAM[0].ClkRstControllerPllmMisc2OverrideEnable = 0x00000000;
+SDRAM[0].ClearClk2Mc1 = 0x00000000;
+SDRAM[0].EmcAutoCalInterval = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig = 0xa01a51d8;
+SDRAM[0].EmcAutoCalConfig2 = 0x05500000;
+SDRAM[0].EmcAutoCalConfig3 = 0x00770000;
+SDRAM[0].EmcAutoCalConfig4 = 0x00770000;
+SDRAM[0].EmcAutoCalConfig5 = 0x00770000;
+SDRAM[0].EmcAutoCalConfig6 = 0x00770000;
+SDRAM[0].EmcAutoCalConfig7 = 0x00770000;
+SDRAM[0].EmcAutoCalConfig8 = 0x00770000;
+SDRAM[0].EmcAutoCalVrefSel0 = 0xb3afa6a6;
+SDRAM[0].EmcAutoCalVrefSel1 = 0x00009e3c;
+SDRAM[0].EmcAutoCalChannel = 0xc1e00303;
+SDRAM[0].EmcPmacroAutocalCfg0 = 0x04040404;
+SDRAM[0].EmcPmacroAutocalCfg1 = 0x04040404;
+SDRAM[0].EmcPmacroAutocalCfg2 = 0x00000000;
+SDRAM[0].EmcPmacroRxTerm = 0x1f1f1f1f;
+SDRAM[0].EmcPmacroDqTxDrv = 0x1f1f1f1f;
+SDRAM[0].EmcPmacroCaTxDrv = 0x1f1f1f1f;
+SDRAM[0].EmcPmacroCmdTxDrv = 0x00001f1f;
+SDRAM[0].EmcPmacroAutocalCfgCommon = 0x00000804;
+SDRAM[0].EmcPmacroZctrl = 0x00000550;
+SDRAM[0].EmcAutoCalWait = 0x000001a1;
+SDRAM[0].EmcXm2CompPadCtrl = 0x00000032;
+SDRAM[0].EmcXm2CompPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2CompPadCtrl3 = 0x00000000;
+SDRAM[0].EmcAdrCfg = 0x00000001;
+SDRAM[0].EmcPinProgramWait = 0x00000002;
+SDRAM[0].EmcPinExtraWait = 0x00000000;
+SDRAM[0].EmcPinGpioEn = 0x00000003;
+SDRAM[0].EmcPinGpio = 0x00000003;
+SDRAM[0].EmcTimingControlWait = 0x0000001e;
+SDRAM[0].EmcRc = 0x0000000d;
+SDRAM[0].EmcRfc = 0x00000025;
+SDRAM[0].EmcRfcPb = 0x00000013;
+SDRAM[0].EmcRefctrl2 = 0x00000000;
+SDRAM[0].EmcRfcSlr = 0x00000000;
+SDRAM[0].EmcRas = 0x00000009;
+SDRAM[0].EmcRp = 0x00000004;
+SDRAM[0].EmcR2r = 0x00000000;
+SDRAM[0].EmcW2w = 0x00000000;
+SDRAM[0].EmcR2w = 0x0000000b;
+SDRAM[0].EmcW2r = 0x0000000d;
+SDRAM[0].EmcR2p = 0x00000008;
+SDRAM[0].EmcW2p = 0x0000000b;
+SDRAM[0].EmcTppd = 0x00000004;
+SDRAM[0].EmcCcdmw = 0x00000020;
+SDRAM[0].EmcRdRcd = 0x00000006;
+SDRAM[0].EmcWrRcd = 0x00000006;
+SDRAM[0].EmcRrd = 0x00000006;
+SDRAM[0].EmcRext = 0x00000003;
+SDRAM[0].EmcWext = 0x00000000;
+SDRAM[0].EmcWdv = 0x00000004;
+SDRAM[0].EmcWdvChk = 0x00000006;
+SDRAM[0].EmcWsv = 0x00000002;
+SDRAM[0].EmcWev = 0x00000000;
+SDRAM[0].EmcWdvMask = 0x00000004;
+SDRAM[0].EmcWsDuration = 0x00000008;
+SDRAM[0].EmcWeDuration = 0x0000000d;
+SDRAM[0].EmcQUse = 0x00000005;
+SDRAM[0].EmcQuseWidth = 0x00000006;
+SDRAM[0].EmcIbdly = 0x00000000;
+SDRAM[0].EmcObdly = 0x00000000;
+SDRAM[0].EmcEInput = 0x00000002;
+SDRAM[0].EmcEInputDuration = 0x0000000d;
+SDRAM[0].EmcPutermExtra = 0x00000002;
+SDRAM[0].EmcPutermWidth = 0x0000000b;
+SDRAM[0].EmcQRst = 0x00010000;
+SDRAM[0].EmcQSafe = 0x00000012;
+SDRAM[0].EmcRdv = 0x00000014;
+SDRAM[0].EmcRdvMask = 0x00000016;
+SDRAM[0].EmcRdvEarly = 0x00000012;
+SDRAM[0].EmcRdvEarlyMask = 0x00000014;
+SDRAM[0].EmcQpop = 0x0000000a;
+SDRAM[0].EmcRefresh = 0x00000304;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt = 0x000000c1;
+SDRAM[0].EmcPdEx2Wr = 0x00000008;
+SDRAM[0].EmcPdEx2Rd = 0x00000008;
+SDRAM[0].EmcPChg2Pden = 0x00000003;
+SDRAM[0].EmcAct2Pden = 0x00000003;
+SDRAM[0].EmcAr2Pden = 0x00000003;
+SDRAM[0].EmcRw2Pden = 0x00000012;
+SDRAM[0].EmcCke2Pden = 0x00000005;
+SDRAM[0].EmcPdex2Cke = 0x00000002;
+SDRAM[0].EmcPdex2Mrr = 0x0000000d;
+SDRAM[0].EmcTxsr = 0x00000027;
+SDRAM[0].EmcTxsrDll = 0x00000027;
+SDRAM[0].EmcTcke = 0x00000005;
+SDRAM[0].EmcTckesr = 0x00000005;
+SDRAM[0].EmcTpd = 0x00000004;
+SDRAM[0].EmcTfaw = 0x00000009;
+SDRAM[0].EmcTrpab = 0x00000005;
+SDRAM[0].EmcTClkStable = 0x00000003;
+SDRAM[0].EmcTClkStop = 0x00000009;
+SDRAM[0].EmcTRefBw = 0x0000031c;
+SDRAM[0].EmcFbioCfg5 = 0x9160a00d;
+SDRAM[0].EmcFbioCfg7 = 0x00003bbf;
+SDRAM[0].EmcFbioCfg8 = 0x0cf30000;
+SDRAM[0].EmcCmdMappingCmd0_0 = 0x07050203;
+SDRAM[0].EmcCmdMappingCmd0_1 = 0x06041b1c;
+SDRAM[0].EmcCmdMappingCmd0_2 = 0x05252523;
+SDRAM[0].EmcCmdMappingCmd1_0 = 0x1e0d0b0a;
+SDRAM[0].EmcCmdMappingCmd1_1 = 0x240c091d;
+SDRAM[0].EmcCmdMappingCmd1_2 = 0x04262608;
+SDRAM[0].EmcCmdMappingCmd2_0 = 0x051b0302;
+SDRAM[0].EmcCmdMappingCmd2_1 = 0x0604231c;
+SDRAM[0].EmcCmdMappingCmd2_2 = 0x09252507;
+SDRAM[0].EmcCmdMappingCmd3_0 = 0x0c0b0d0a;
+SDRAM[0].EmcCmdMappingCmd3_1 = 0x08091e1d;
+SDRAM[0].EmcCmdMappingCmd3_2 = 0x08262624;
+SDRAM[0].EmcCmdMappingByte = 0x0a270623;
+SDRAM[0].EmcFbioSpare = 0x00000012;
+SDRAM[0].EmcCfgRsv = 0xff00ff00;
+SDRAM[0].EmcMrs = 0x00000000;
+SDRAM[0].EmcEmrs = 0x00000000;
+SDRAM[0].EmcEmrs2 = 0x00000000;
+SDRAM[0].EmcEmrs3 = 0x00000000;
+SDRAM[0].EmcMrw1 = 0x08010004;
+SDRAM[0].EmcMrw2 = 0x08020000;
+SDRAM[0].EmcMrw3 = 0x080d0000;
+SDRAM[0].EmcMrw4 = 0xc0000000;
+SDRAM[0].EmcMrw6 = 0x08037171;
+SDRAM[0].EmcMrw8 = 0x080b0000;
+SDRAM[0].EmcMrw9 = 0x0c0e6b6b;
+SDRAM[0].EmcMrw10 = 0x00000000;
+SDRAM[0].EmcMrw12 = 0x0c0d0808;
+SDRAM[0].EmcMrw13 = 0x0c0d0000;
+SDRAM[0].EmcMrw14 = 0x08161414;
+SDRAM[0].EmcMrwExtra = 0x08010004;
+SDRAM[0].EmcWarmBootMrwExtra = 0x08110000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000001;
+SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt = 0x00cc0015;
+SDRAM[0].EmcMrsWaitCnt2 = 0x0033000a;
+SDRAM[0].EmcCfg = 0xf3200000;
+SDRAM[0].EmcCfg2 = 0x00110805;
+SDRAM[0].EmcCfgPipe = 0x0fff0fff;
+SDRAM[0].EmcCfgPipeClk = 0x00000000;
+SDRAM[0].EmcFdpdCtrlCmdNoRamp = 0x00000001;
+SDRAM[0].EmcCfgUpdate = 0x70000301;
+SDRAM[0].EmcDbg = 0x01000c00;
+SDRAM[0].EmcDbgWriteMux = 0x00000001;
+SDRAM[0].EmcCmdQ = 0x10004408;
+SDRAM[0].EmcMc2EmcQ = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl = 0x80000713;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[0].EmcCfgDigDll = 0x002c00a0;
+SDRAM[0].EmcCfgDigDll_1 = 0x00003701;
+SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[0].EmcDevSelect = 0x00000000;
+SDRAM[0].EmcSelDpdCtrl = 0x00040008;
+SDRAM[0].EmcFdpdCtrlDq = 0x8020221f;
+SDRAM[0].EmcFdpdCtrlCmd = 0x0220f40f;
+SDRAM[0].EmcPmacroIbVrefDq_0 = 0x28282828;
+SDRAM[0].EmcPmacroIbVrefDq_1 = 0x28282828;
+SDRAM[0].EmcPmacroIbVrefDqs_0 = 0x11111111;
+SDRAM[0].EmcPmacroIbVrefDqs_1 = 0x11111111;
+SDRAM[0].EmcPmacroIbRxrt = 0x000000be;
+SDRAM[0].EmcCfgPipe1 = 0x0fff0fff;
+SDRAM[0].EmcCfgPipe2 = 0x0fff0fff;
+SDRAM[0].EmcPmacroQuseDdllRank0_0 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank0_1 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank0_2 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank0_3 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank0_4 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank0_5 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank1_0 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank1_1 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank1_2 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank1_3 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank1_4 = 0x00000000;
+SDRAM[0].EmcPmacroQuseDdllRank1_5 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank0_0 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank0_1 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank0_2 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank0_3 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank0_4 = 0x00080007;
+SDRAM[0].EmcPmacroObDdllLongDqRank0_5 = 0x00090006;
+SDRAM[0].EmcPmacroObDdllLongDqRank1_0 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank1_1 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank1_2 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank1_3 = 0x00000000;
+SDRAM[0].EmcPmacroObDdllLongDqRank1_4 = 0x00080007;
+SDRAM[0].EmcPmacroObDdllLongDqRank1_5 = 0x00090006;
+SDRAM[0].EmcPmacroObDdllLongDqsRank0_0 = 0x00340033;
+SDRAM[0].EmcPmacroObDdllLongDqsRank0_1 = 0x00340037;
+SDRAM[0].EmcPmacroObDdllLongDqsRank0_2 = 0x00360037;
+SDRAM[0].EmcPmacroObDdllLongDqsRank0_3 = 0x00330036;
+SDRAM[0].EmcPmacroObDdllLongDqsRank0_4 = 0x000a000c;
+SDRAM[0].EmcPmacroObDdllLongDqsRank0_5 = 0x000d000a;
+SDRAM[0].EmcPmacroObDdllLongDqsRank1_0 = 0x00340033;
+SDRAM[0].EmcPmacroObDdllLongDqsRank1_1 = 0x00340037;
+SDRAM[0].EmcPmacroObDdllLongDqsRank1_2 = 0x00360037;
+SDRAM[0].EmcPmacroObDdllLongDqsRank1_3 = 0x00330036;
+SDRAM[0].EmcPmacroObDdllLongDqsRank1_4 = 0x000a000c;
+SDRAM[0].EmcPmacroObDdllLongDqsRank1_5 = 0x000d000a;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank0_0 = 0x00F000F0;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank0_1 = 0x00F000F0;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank0_2 = 0x00F000F0;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank0_3 = 0x00F000F0;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank1_0 = 0x00F000F0;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank1_1 = 0x00F000F0;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank1_2 = 0x00F000F0;
+SDRAM[0].EmcPmacroIbDdllLongDqsRank1_3 = 0x00F000F0;
+SDRAM[0].EmcPmacroDdllLongCmd_0 = 0x00070007;
+SDRAM[0].EmcPmacroDdllLongCmd_1 = 0x00080008;
+SDRAM[0].EmcPmacroDdllLongCmd_2 = 0x00060006;
+SDRAM[0].EmcPmacroDdllLongCmd_3 = 0x00090009;
+SDRAM[0].EmcPmacroDdllLongCmd_4 = 0x00000007;
+SDRAM[0].EmcPmacroDdllShortCmd_0 = 0x00000000;
+SDRAM[0].EmcPmacroDdllShortCmd_1 = 0x00000000;
+SDRAM[0].EmcPmacroDdllShortCmd_2 = 0x00000000;
+SDRAM[0].WarmBootWait = 0x00000001;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcZcalInterval = 0x00064000;
+SDRAM[0].EmcZcalWaitCnt = 0x000900cc;
+SDRAM[0].EmcZcalMrwCmd = 0x0051004f;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcZcalInitDev0 = 0x80000001;
+SDRAM[0].EmcZcalInitDev1 = 0x40000001;
+SDRAM[0].EmcZcalInitWait = 0x00000001;
+SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[0].EmcZqCalLpDdr4WarmBoot = 0x00000001;
+SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcMrsExtra = 0x00000000;
+SDRAM[0].EmcWarmBootMrsExtra = 0x00000000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[0].EmcDdr2Wait = 0x00000000;
+SDRAM[0].EmcClkenOverride = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[0].PmcVddpSel = 0x00000001;
+SDRAM[0].PmcVddpSelWait = 0x00000002;
+SDRAM[0].PmcDdrPwr = 0x0000000f;
+SDRAM[0].PmcDdrCfg = 0x20120100;
+SDRAM[0].PmcIoDpd3Req = 0x4befffff;
+SDRAM[0].PmcIoDpd3ReqWait = 0x00000001;
+SDRAM[0].PmcIoDpd4ReqWait = 0x00000002;
+SDRAM[0].PmcRegShort = 0x00000000;
+SDRAM[0].PmcNoIoPower = 0x00000000;
+SDRAM[0].PmcDdrCntrlWait = 0x00000000;
+SDRAM[0].PmcDdrCntrl = 0x0007ff8b;
+SDRAM[0].EmcAcpdControl = 0x00000000;
+SDRAM[0].EmcSwizzleRank0Byte0 = 0x71245603;
+SDRAM[0].EmcSwizzleRank0Byte1 = 0x16243705;
+SDRAM[0].EmcSwizzleRank0Byte2 = 0x12574630;
+SDRAM[0].EmcSwizzleRank0Byte3 = 0x26147503;
+SDRAM[0].EmcSwizzleRank1Byte0 = 0x71345602;
+SDRAM[0].EmcSwizzleRank1Byte1 = 0x20456713;
+SDRAM[0].EmcSwizzleRank1Byte2 = 0x64071325;
+SDRAM[0].EmcSwizzleRank1Byte3 = 0x54023167;
+SDRAM[0].EmcTxdsrvttgen = 0x00000000;
+SDRAM[0].EmcDataBrlshft0 = 0x00249249;
+SDRAM[0].EmcDataBrlshft1 = 0x00249249;
+SDRAM[0].EmcDqsBrlshft0 = 0x00000000;
+SDRAM[0].EmcDqsBrlshft1 = 0x00000000;
+SDRAM[0].EmcCmdBrlshft0 = 0x00000000;
+SDRAM[0].EmcCmdBrlshft1 = 0x00000000;
+SDRAM[0].EmcCmdBrlshft2 = 0x00000012;
+SDRAM[0].EmcCmdBrlshft3 = 0x00000012;
+SDRAM[0].EmcQuseBrlshft0 = 0x00000000;
+SDRAM[0].EmcQuseBrlshft1 = 0x00000000;
+SDRAM[0].EmcQuseBrlshft2 = 0x00000000;
+SDRAM[0].EmcQuseBrlshft3 = 0x00000000;
+SDRAM[0].EmcDllCfg0 = 0x1f13412f;
+SDRAM[0].EmcDllCfg1 = 0x00010014;
+SDRAM[0].EmcPmcScratch1 = 0x4befffff;
+SDRAM[0].EmcPmcScratch2 = 0x7fffffff;
+SDRAM[0].EmcPmcScratch3 = 0x4005d70b;
+SDRAM[0].EmcPmacroPadCfgCtrl = 0x00020000;
+SDRAM[0].EmcPmacroVttgenCtrl0 = 0x00030808;
+SDRAM[0].EmcPmacroVttgenCtrl1 = 0x00015000;
+SDRAM[0].EmcPmacroVttgenCtrl2 = 0x00101010;
+SDRAM[0].EmcPmacroBrickCtrlRfu1 = 0x00001600;
+SDRAM[0].EmcPmacroCmdBrickCtrlFdpd = 0x00000000;
+SDRAM[0].EmcPmacroBrickCtrlRfu2 = 0x00000000;
+SDRAM[0].EmcPmacroDataBrickCtrlFdpd = 0x00000000;
+SDRAM[0].EmcPmacroBgBiasCtrl0 = 0x00000030;
+SDRAM[0].EmcPmacroDataPadRxCtrl = 0x10050037;
+SDRAM[0].EmcPmacroCmdPadRxCtrl = 0x00000000;
+SDRAM[0].EmcPmacroDataRxTermMode = 0x00000010;
+SDRAM[0].EmcPmacroCmdRxTermMode = 0x00003000;
+SDRAM[0].EmcPmacroDataPadTxCtrl = 0x02000111;
+SDRAM[0].EmcPmacroCommonPadTxCtrl = 0x00000008;
+SDRAM[0].EmcPmacroCmdPadTxCtrl = 0x0a000000;
+SDRAM[0].EmcCfg3 = 0x00000040;
+SDRAM[0].EmcPmacroTxPwrd0 = 0x10000000;
+SDRAM[0].EmcPmacroTxPwrd1 = 0x08000000;
+SDRAM[0].EmcPmacroTxPwrd2 = 0x10000000;
+SDRAM[0].EmcPmacroTxPwrd3 = 0x08000000;
+SDRAM[0].EmcPmacroTxPwrd4 = 0x00000000;
+SDRAM[0].EmcPmacroTxPwrd5 = 0x00000000;
+SDRAM[0].EmcConfigSampleDelay = 0x00000020;
+SDRAM[0].EmcPmacroBrickMapping0 = 0x28190081;
+SDRAM[0].EmcPmacroBrickMapping1 = 0x44853293;
+SDRAM[0].EmcPmacroBrickMapping2 = 0x76a76a5b;
+SDRAM[0].EmcPmacroTxSelClkSrc0 = 0x00000000;
+SDRAM[0].EmcPmacroTxSelClkSrc1 = 0x00000000;
+SDRAM[0].EmcPmacroTxSelClkSrc2 = 0x00000000;
+SDRAM[0].EmcPmacroTxSelClkSrc3 = 0x00000000;
+SDRAM[0].EmcPmacroTxSelClkSrc4 = 0x00000000;
+SDRAM[0].EmcPmacroTxSelClkSrc5 = 0x00000000;
+SDRAM[0].EmcPmacroDdllBypass = 0xefffefff;
+SDRAM[0].EmcPmacroDdllPwrd0 = 0xc0c0c0c0;
+SDRAM[0].EmcPmacroDdllPwrd1 = 0xc0c0c0c0;
+SDRAM[0].EmcPmacroDdllPwrd2 = 0xdcdcdcdc;
+SDRAM[0].EmcPmacroCmdCtrl0 = 0x0a0a0a0a;
+SDRAM[0].EmcPmacroCmdCtrl1 = 0x0a0a0a0a;
+SDRAM[0].EmcPmacroCmdCtrl2 = 0x0a0a0a0a;
+SDRAM[0].McEmemAdrCfg = 0x00000001;
+SDRAM[0].McEmemAdrCfgDev0 = 0x000d0302;
+SDRAM[0].McEmemAdrCfgDev1 = 0x000d0302;
+SDRAM[0].McEmemAdrCfgChannelMask = 0xffff2400;
+SDRAM[0].McEmemAdrCfgBankMask0 = 0x6e574400;
+SDRAM[0].McEmemAdrCfgBankMask1 = 0x39722800;
+SDRAM[0].McEmemAdrCfgBankMask2 = 0x4b9c1000;
+SDRAM[0].McEmemCfg = 0x00000c00;
+SDRAM[0].McEmemArbCfg = 0x08000001;
+SDRAM[0].McEmemArbOutstandingReq = 0x8000004c;
+SDRAM[0].McEmemArbRefpbHpCtrl = 0x000a1020;
+SDRAM[0].McEmemArbRefpbBankCtrl = 0x80001028;
+SDRAM[0].McEmemArbTimingRcd = 0x00000001;
+SDRAM[0].McEmemArbTimingRp = 0x00000000;
+SDRAM[0].McEmemArbTimingRc = 0x00000003;
+SDRAM[0].McEmemArbTimingRas = 0x00000001;
+SDRAM[0].McEmemArbTimingFaw = 0x00000002;
+SDRAM[0].McEmemArbTimingRrd = 0x00000001;
+SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[0].McEmemArbTimingWap2Pre = 0x00000005;
+SDRAM[0].McEmemArbTimingR2R = 0x00000001;
+SDRAM[0].McEmemArbTimingW2W = 0x00000001;
+SDRAM[0].McEmemArbTimingR2W = 0x00000004;
+SDRAM[0].McEmemArbTimingW2R = 0x00000005;
+SDRAM[0].McEmemArbTimingRFCPB = 0x00000004;
+SDRAM[0].McEmemArbDaTurns = 0x02020000;
+SDRAM[0].McEmemArbDaCovers = 0x00030201;
+SDRAM[0].McEmemArbMisc0 = 0x71c30504;
+SDRAM[0].McEmemArbMisc1 = 0x70000f0f;
+SDRAM[0].McEmemArbMisc2 = 0x00000000;
+SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[0].McEmemArbOverride = 0x10000000;
+SDRAM[0].McEmemArbOverride1 = 0x00000000;
+SDRAM[0].McEmemArbRsv = 0xff00ff00;
+SDRAM[0].McDaCfg0 = 0x00000001;
+SDRAM[0].McEmemArbTimingCcdmw = 0x00000008;
+SDRAM[0].McClkenOverride = 0x00008000;
+SDRAM[0].McStatControl = 0x00000000;
+SDRAM[0].McVideoProtectBom = 0xfff00000;
+SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[0].McVideoProtectSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectVprOverride = 0xe4bac343;
+SDRAM[0].McVideoProtectVprOverride1 = 0x00001ed3;
+SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[0].McSecCarveoutBom = 0xfff00000;
+SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1Bom = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1BomHi = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1Size128kb = 0x00000008;
+SDRAM[0].McGeneralizedCarveout1Access0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1Access1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1Access2 = 0x00300000;
+SDRAM[0].McGeneralizedCarveout1Access3 = 0x03000000;
+SDRAM[0].McGeneralizedCarveout1Access4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1ForceInternalAccess0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1ForceInternalAccess1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1ForceInternalAccess2 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1ForceInternalAccess3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1ForceInternalAccess4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout1Cfg0 = 0x04000c75;
+SDRAM[0].McGeneralizedCarveout2Bom = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2BomHi = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2Size128kb = 0x00000002;
+SDRAM[0].McGeneralizedCarveout2Access0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2Access1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2Access2 = 0x03000000;
+SDRAM[0].McGeneralizedCarveout2Access3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2Access4 = 0x00000300;
+SDRAM[0].McGeneralizedCarveout2ForceInternalAccess0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2ForceInternalAccess1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2ForceInternalAccess2 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2ForceInternalAccess3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2ForceInternalAccess4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout2Cfg0 = 0x0440167c;
+SDRAM[0].McGeneralizedCarveout3Bom = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3BomHi = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3Size128kb = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3Access0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3Access1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3Access2 = 0x03000000;
+SDRAM[0].McGeneralizedCarveout3Access3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3Access4 = 0x00000300;
+SDRAM[0].McGeneralizedCarveout3ForceInternalAccess0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3ForceInternalAccess1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3ForceInternalAccess2 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3ForceInternalAccess3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3ForceInternalAccess4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout3Cfg0 = 0x04401e7c;
+SDRAM[0].McGeneralizedCarveout4Bom = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4BomHi = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4Size128kb = 0x00000008;
+SDRAM[0].McGeneralizedCarveout4Access0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4Access1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4Access2 = 0x00300000;
+SDRAM[0].McGeneralizedCarveout4Access3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4Access4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4ForceInternalAccess0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4ForceInternalAccess1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout4Cfg0 = 0x04002442;
+SDRAM[0].McGeneralizedCarveout5Bom = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5BomHi = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5Size128kb = 0x00000008;
+SDRAM[0].McGeneralizedCarveout5Access0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5Access1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5Access2 = 0x00300000;
+SDRAM[0].McGeneralizedCarveout5Access3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5Access4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5ForceInternalAccess0 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5ForceInternalAccess1 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000;
+SDRAM[0].McGeneralizedCarveout5Cfg0 = 0x04002c42;
+SDRAM[0].EmcCaTrainingEnable = 0x00000000;
+SDRAM[0].SwizzleRankByteEncode = 0x0000000e;
+SDRAM[0].BootRomPatchControl = 0x00000000;
+SDRAM[0].BootRomPatchData = 0x00000000;
+SDRAM[0].McMtsCarveoutBom = 0xfff00000;
+SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
+SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
+SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 {0x7001b800} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 {0x7001b804} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 {0x7001b808} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 {0x7001b80c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 {0x7001b810} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 {0x7001b814} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 {0x7001b818} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 {0x7001b81c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 {0x7001b820} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 {0x7001b824} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 {0x7001b828} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 {0x7001b82c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 {0x7001b830} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 {0x7001b834} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 {0x7001b838} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 {0x7001b83c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 {0x7001b840} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 {0x7001b844} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 {0x7001b848} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 {0x7001b84c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 {0x7001b850} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 {0x7001b854} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 {0x7001b858} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 {0x7001b85c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 {0x7001b860} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 {0x7001b864} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 {0x7001b868} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 {0x7001b86c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 {0x7001b870} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 {0x7001b874} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 {0x7001b878} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 {0x7001b87c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 {0x7001b880} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 {0x7001b884} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 {0x7001b888} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 {0x7001b88c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 {0x7001b890} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 {0x7001b894} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 {0x7001b898} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 {0x7001b89c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 {0x7001b8a0} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 {0x7001b8a4} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 {0x7001b8a8} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 {0x7001b8ac} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 {0x7001b8b0} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 {0x7001b8b4} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 {0x7001b8b8} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 {0x7001b8bc} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 {0x7001b900} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 {0x7001b904} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 {0x7001b908} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 {0x7001b90c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 {0x7001b910} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 {0x7001b914} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 {0x7001b918} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 {0x7001b91c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 {0x7001b920} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 {0x7001b924} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 {0x7001b928} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 {0x7001b92c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 {0x7001b930} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 {0x7001b934} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 {0x7001b938} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 {0x7001b93c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 {0x7001b940} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 {0x7001b944} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 {0x7001b948} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 {0x7001b94c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 {0x7001b950} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 {0x7001b954} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 {0x7001b958} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 {0x7001b95c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 {0x7001b960} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 {0x7001b964} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 {0x7001b968} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 {0x7001b96c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 {0x7001b970} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 {0x7001b974} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 {0x7001b978} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 {0x7001b97c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 {0x7001b980} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 {0x7001b984} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 {0x7001b988} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 {0x7001b98c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 {0x7001b990} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 {0x7001b994} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 {0x7001b998} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 {0x7001b99c} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 {0x7001b9a0} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 {0x7001b9a4} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 {0x7001b9a8} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 {0x7001b9ac} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 {0x7001b9b0} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 {0x7001b9b4} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 {0x7001b9b8} = 0x00000000;
+#@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 {0x7001b9bc} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 {0x7001ba00} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 {0x7001ba04} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 {0x7001ba08} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 {0x7001ba10} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 {0x7001ba14} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 {0x7001ba18} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 {0x7001ba20} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 {0x7001ba24} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 {0x7001ba28} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 {0x7001ba30} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 {0x7001ba34} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 {0x7001ba38} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 {0x7001ba40} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 {0x7001ba44} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 {0x7001ba48} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 {0x7001ba50} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 {0x7001ba54} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 {0x7001ba58} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 {0x7001ba60} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 {0x7001ba64} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 {0x7001ba68} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 {0x7001ba70} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 {0x7001ba74} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 {0x7001ba78} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 {0x7001bb00} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 {0x7001bb04} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 {0x7001bb08} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 {0x7001bb10} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 {0x7001bb14} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 {0x7001bb18} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 {0x7001bb20} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 {0x7001bb24} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 {0x7001bb28} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 {0x7001bb30} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 {0x7001bb34} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 {0x7001bb38} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 {0x7001bb40} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 {0x7001bb44} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 {0x7001bb48} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 {0x7001bb50} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 {0x7001bb54} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 {0x7001bb58} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 {0x7001bb60} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 {0x7001bb64} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 {0x7001bb68} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 {0x7001bb70} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 {0x7001bb74} = 0x00000000;
+#@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 {0x7001bb78} = 0x00000000;
+#@ EMC_TR_TIMING_0 {0x7001b3b4} = 0x01186033;
+#@ EMC_TR_DVFS {0x7001b460} = 0x00000000;
+#@ EMC_TR_CTRL_1 {0x7001b3bc} = 0x00000000;
+#@ EMC_TR_RDV {0x7001b3c4} = 0x00000014;
+#@ EMC_TR_QPOP {0x7001b3f4} = 0x0000000a;
+#@ EMC_TR_RDV_MASK {0x7001b3f8} = 0x00000016;
+#@ EMC_TR_QSAFE {0x7001b3fc} = 0x00000012;
+#@ EMC_TR_QRST {0x7001b400} = 0x00010000;
+#@ EMC_TRAINING_CTRL {0x7001be04} = 0x00009080;
+#@ EMC_TRAINING_SETTLE {0x7001be44} = 0x07070404;
+#@ EMC_TRAINING_VREF_SETTLE {0x7001be6c} = 0x00040065;
+#@ EMC_TRAINING_CA_FINE_CTRL {0x7001be30} = 0x0513801f;
+#@ EMC_TRAINING_CA_CTRL_MISC {0x7001be34} = 0x1f101100;
+#@ EMC_TRAINING_CA_CTRL_MISC1 {0x7001be38} = 0x00000014;
+#@ EMC_TRAINING_CA_VREF_CTRL {0x7001be3c} = 0x00107240;
+#@ EMC_TRAINING_QUSE_CORS_CTRL {0x7001be0c} = 0x01124000;
+#@ EMC_TRAINING_QUSE_FINE_CTRL {0x7001be10} = 0x01125b6a;
+#@ EMC_TRAINING_QUSE_CTRL_MISC {0x7001be14} = 0x0f081000;
+#@ EMC_TRAINING_QUSE_VREF_CTRL {0x7001bed0} = 0x00105800;
+#@ EMC_TRAINING_READ_FINE_CTRL {0x7001be24} = 0x1110fc00;
+#@ EMC_TRAINING_READ_CTRL_MISC {0x7001be28} = 0x0f081300;
+#@ EMC_TRAINING_READ_VREF_CTRL {0x7001be2c} = 0x00105800;
+#@ EMC_TRAINING_WRITE_FINE_CTRL {0x7001be18} = 0x1114fc00;
+#@ EMC_TRAINING_WRITE_CTRL_MISC {0x7001be1c} = 0x07000300;
+#@ EMC_TRAINING_WRITE_VREF_CTRL {0x7001be20} = 0x00107240;
+#@ EMC_TRAINING_MPC {0x7001be5c} = 0x55553c5a;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000001b;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000024c;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00ff00b2;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00ff00da;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00ff009d;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00ff00ff;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00ff000c;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00ff00ff;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00ff000c;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x007f0049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00ff0080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00ff0004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x000800ad;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000ff;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00ff0004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00ff00c6;
+#@ MC_LATENCY_ALLOWANCE_GPU2_0 {0x700193e8} = 0x00ff00c6;
+#@ MC_LATENCY_ALLOWANCE_NVENC_0 {0x70019328} = 0x00ff006d;
+#@ MC_LATENCY_ALLOWANCE_NVDEC_0 {0x700193d8} = 0x00ff00ff;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00ff00e2;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000ff;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000080;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00ff00ff;
+#@ MC_LATENCY_ALLOWANCE_NVJPG_0 {0x700193e4} = 0x00ff00ea;
+#@ MC_LATENCY_ALLOWANCE_APE_0 {0x700193dc} = 0x00ff00ff;
+#@ MC_LATENCY_ALLOWANCE_TSECB_0 {0x700193f0} = 0x00ff009d;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000080;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00ff00ff;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00ff00ff;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00ff00da;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00ff0024;
+#@ EMC_MRW10_CH0 {0x7001e4b4} = 0x880c6b6b;
+#@ EMC_MRW10_CH1 {0x7001f4b4} = 0x880c6b6b;
+#@ EMC_MRW11_CH0 {0x7001e4b8} = 0x480c6b6b;
+#@ EMC_MRW11_CH1 {0x7001f4b8} = 0x480c6b6b;
+#@ tPDEX [dvfs dram_timing] = 0x00000018;
+#@ tRP [dvfs dram_timing] = 0x00000012;
+#@ tRFC [dvfs dram_timing] = 0x000000b4;
+#@ tFC_lpddr4 [dvfs dram_timing hard_coded] = 0x00000104;
+#@ RL [dvfs dram_timing] = 0x00000006;
+
diff --git a/src/mainboard/google/foster/bct/sdram-samsung-3GB-204.inc b/src/mainboard/google/foster/bct/sdram-samsung-3GB-204.inc
new file mode 100644
index 0000000000..29d55c9121
--- /dev/null
+++ b/src/mainboard/google/foster/bct/sdram-samsung-3GB-204.inc
@@ -0,0 +1,477 @@
+{ /* generated from sdram-samsung-3GB-204.cfg; do not edit. */
+ .MemoryType = NvBootMemoryType_LpDdr4,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x00000022,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMPostDivider = 0x00000000,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x7001bc3c,
+ .EmcBctSpare5 = 0x00000032,
+ .EmcBctSpare6 = 0x7001b404,
+ .EmcBctSpare7 = 0x71245603,
+ .EmcBctSpare8 = 0x7000e6c8,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcBctSpare12 = 0x7001bc3c,
+ .EmcBctSpare13 = 0x00000033,
+ .EmcClockSource = 0x40188002,
+ .EmcClockSourceDll = 0x40000000,
+ .ClkRstControllerPllmMisc2Override = 0x00000000,
+ .ClkRstControllerPllmMisc2OverrideEnable = 0x00000000,
+ .ClearClk2Mc1 = 0x00000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa01a51d8,
+ .EmcAutoCalConfig2 = 0x05500000,
+ .EmcAutoCalConfig3 = 0x00770000,
+ .EmcAutoCalConfig4 = 0x00770000,
+ .EmcAutoCalConfig5 = 0x00770000,
+ .EmcAutoCalConfig6 = 0x00770000,
+ .EmcAutoCalConfig7 = 0x00770000,
+ .EmcAutoCalConfig8 = 0x00770000,
+ .EmcAutoCalVrefSel0 = 0xb3afa6a6,
+ .EmcAutoCalVrefSel1 = 0x00009e3c,
+ .EmcAutoCalChannel = 0xc1e00303,
+ .EmcPmacroAutocalCfg0 = 0x04040404,
+ .EmcPmacroAutocalCfg1 = 0x04040404,
+ .EmcPmacroAutocalCfg2 = 0x00000000,
+ .EmcPmacroRxTerm = 0x1f1f1f1f,
+ .EmcPmacroDqTxDrv = 0x1f1f1f1f,
+ .EmcPmacroCaTxDrv = 0x1f1f1f1f,
+ .EmcPmacroCmdTxDrv = 0x00001f1f,
+ .EmcPmacroAutocalCfgCommon = 0x00000804,
+ .EmcPmacroZctrl = 0x00000550,
+ .EmcAutoCalWait = 0x000001a1,
+ .EmcXm2CompPadCtrl = 0x00000032,
+ .EmcXm2CompPadCtrl2 = 0x00000000,
+ .EmcXm2CompPadCtrl3 = 0x00000000,
+ .EmcAdrCfg = 0x00000001,
+ .EmcPinProgramWait = 0x00000002,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcPinGpioEn = 0x00000003,
+ .EmcPinGpio = 0x00000003,
+ .EmcTimingControlWait = 0x0000001e,
+ .EmcRc = 0x0000000d,
+ .EmcRfc = 0x00000025,
+ .EmcRfcPb = 0x00000013,
+ .EmcRefctrl2 = 0x00000000,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x00000009,
+ .EmcRp = 0x00000004,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x0000000b,
+ .EmcW2r = 0x0000000d,
+ .EmcR2p = 0x00000008,
+ .EmcW2p = 0x0000000b,
+ .EmcTppd = 0x00000004,
+ .EmcCcdmw = 0x00000020,
+ .EmcRdRcd = 0x00000006,
+ .EmcWrRcd = 0x00000006,
+ .EmcRrd = 0x00000006,
+ .EmcRext = 0x00000003,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000004,
+ .EmcWdvChk = 0x00000006,
+ .EmcWsv = 0x00000002,
+ .EmcWev = 0x00000000,
+ .EmcWdvMask = 0x00000004,
+ .EmcWsDuration = 0x00000008,
+ .EmcWeDuration = 0x0000000d,
+ .EmcQUse = 0x00000005,
+ .EmcQuseWidth = 0x00000006,
+ .EmcIbdly = 0x00000000,
+ .EmcObdly = 0x00000000,
+ .EmcEInput = 0x00000002,
+ .EmcEInputDuration = 0x0000000d,
+ .EmcPutermExtra = 0x00000002,
+ .EmcPutermWidth = 0x0000000b,
+ .EmcQRst = 0x00010000,
+ .EmcQSafe = 0x00000012,
+ .EmcRdv = 0x00000014,
+ .EmcRdvMask = 0x00000016,
+ .EmcRdvEarly = 0x00000012,
+ .EmcRdvEarlyMask = 0x00000014,
+ .EmcQpop = 0x0000000a,
+ .EmcRefresh = 0x00000304,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000000c1,
+ .EmcPdEx2Wr = 0x00000008,
+ .EmcPdEx2Rd = 0x00000008,
+ .EmcPChg2Pden = 0x00000003,
+ .EmcAct2Pden = 0x00000003,
+ .EmcAr2Pden = 0x00000003,
+ .EmcRw2Pden = 0x00000012,
+ .EmcCke2Pden = 0x00000005,
+ .EmcPdex2Cke = 0x00000002,
+ .EmcPdex2Mrr = 0x0000000d,
+ .EmcTxsr = 0x00000027,
+ .EmcTxsrDll = 0x00000027,
+ .EmcTcke = 0x00000005,
+ .EmcTckesr = 0x00000005,
+ .EmcTpd = 0x00000004,
+ .EmcTfaw = 0x00000009,
+ .EmcTrpab = 0x00000005,
+ .EmcTClkStable = 0x00000003,
+ .EmcTClkStop = 0x00000009,
+ .EmcTRefBw = 0x0000031c,
+ .EmcFbioCfg5 = 0x9160a00d,
+ .EmcFbioCfg7 = 0x00003bbf,
+ .EmcFbioCfg8 = 0x0cf30000,
+ .EmcCmdMappingCmd0_0 = 0x07050203,
+ .EmcCmdMappingCmd0_1 = 0x06041b1c,
+ .EmcCmdMappingCmd0_2 = 0x05252523,
+ .EmcCmdMappingCmd1_0 = 0x1e0d0b0a,
+ .EmcCmdMappingCmd1_1 = 0x240c091d,
+ .EmcCmdMappingCmd1_2 = 0x04262608,
+ .EmcCmdMappingCmd2_0 = 0x051b0302,
+ .EmcCmdMappingCmd2_1 = 0x0604231c,
+ .EmcCmdMappingCmd2_2 = 0x09252507,
+ .EmcCmdMappingCmd3_0 = 0x0c0b0d0a,
+ .EmcCmdMappingCmd3_1 = 0x08091e1d,
+ .EmcCmdMappingCmd3_2 = 0x08262624,
+ .EmcCmdMappingByte = 0x0a270623,
+ .EmcFbioSpare = 0x00000012,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x00000000,
+ .EmcEmrs = 0x00000000,
+ .EmcEmrs2 = 0x00000000,
+ .EmcEmrs3 = 0x00000000,
+ .EmcMrw1 = 0x08010004,
+ .EmcMrw2 = 0x08020000,
+ .EmcMrw3 = 0x080d0000,
+ .EmcMrw4 = 0xc0000000,
+ .EmcMrw6 = 0x08037171,
+ .EmcMrw8 = 0x080b0000,
+ .EmcMrw9 = 0x0c0e6b6b,
+ .EmcMrw10 = 0x00000000,
+ .EmcMrw12 = 0x0c0d0808,
+ .EmcMrw13 = 0x0c0d0000,
+ .EmcMrw14 = 0x08161414,
+ .EmcMrwExtra = 0x08010004,
+ .EmcWarmBootMrwExtra = 0x08110000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000001,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x00cc0015,
+ .EmcMrsWaitCnt2 = 0x0033000a,
+ .EmcCfg = 0xf3200000,
+ .EmcCfg2 = 0x00110805,
+ .EmcCfgPipe = 0x0fff0fff,
+ .EmcCfgPipeClk = 0x00000000,
+ .EmcFdpdCtrlCmdNoRamp = 0x00000001,
+ .EmcCfgUpdate = 0x70000301,
+ .EmcDbg = 0x01000c00,
+ .EmcDbgWriteMux = 0x00000001,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x80000713,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0x002c00a0,
+ .EmcCfgDigDll_1 = 0x00003701,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000000,
+ .EmcSelDpdCtrl = 0x00040008,
+ .EmcFdpdCtrlDq = 0x8020221f,
+ .EmcFdpdCtrlCmd = 0x0220f40f,
+ .EmcPmacroIbVrefDq_0 = 0x28282828,
+ .EmcPmacroIbVrefDq_1 = 0x28282828,
+ .EmcPmacroIbVrefDqs_0 = 0x11111111,
+ .EmcPmacroIbVrefDqs_1 = 0x11111111,
+ .EmcPmacroIbRxrt = 0x000000be,
+ .EmcCfgPipe1 = 0x0fff0fff,
+ .EmcCfgPipe2 = 0x0fff0fff,
+ .EmcPmacroQuseDdllRank0_0 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_1 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_2 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_3 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_4 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_5 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_0 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_1 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_2 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_3 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_4 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_5 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_0 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_1 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_2 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_3 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_4 = 0x00080007,
+ .EmcPmacroObDdllLongDqRank0_5 = 0x00090006,
+ .EmcPmacroObDdllLongDqRank1_0 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_1 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_2 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_3 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_4 = 0x00080007,
+ .EmcPmacroObDdllLongDqRank1_5 = 0x00090006,
+ .EmcPmacroObDdllLongDqsRank0_0 = 0x00340033,
+ .EmcPmacroObDdllLongDqsRank0_1 = 0x00340037,
+ .EmcPmacroObDdllLongDqsRank0_2 = 0x00360037,
+ .EmcPmacroObDdllLongDqsRank0_3 = 0x00330036,
+ .EmcPmacroObDdllLongDqsRank0_4 = 0x000a000c,
+ .EmcPmacroObDdllLongDqsRank0_5 = 0x000d000a,
+ .EmcPmacroObDdllLongDqsRank1_0 = 0x00340033,
+ .EmcPmacroObDdllLongDqsRank1_1 = 0x00340037,
+ .EmcPmacroObDdllLongDqsRank1_2 = 0x00360037,
+ .EmcPmacroObDdllLongDqsRank1_3 = 0x00330036,
+ .EmcPmacroObDdllLongDqsRank1_4 = 0x000a000c,
+ .EmcPmacroObDdllLongDqsRank1_5 = 0x000d000a,
+ .EmcPmacroIbDdllLongDqsRank0_0 = 0x00F000F0,
+ .EmcPmacroIbDdllLongDqsRank0_1 = 0x00F000F0,
+ .EmcPmacroIbDdllLongDqsRank0_2 = 0x00F000F0,
+ .EmcPmacroIbDdllLongDqsRank0_3 = 0x00F000F0,
+ .EmcPmacroIbDdllLongDqsRank1_0 = 0x00F000F0,
+ .EmcPmacroIbDdllLongDqsRank1_1 = 0x00F000F0,
+ .EmcPmacroIbDdllLongDqsRank1_2 = 0x00F000F0,
+ .EmcPmacroIbDdllLongDqsRank1_3 = 0x00F000F0,
+ .EmcPmacroDdllLongCmd_0 = 0x00070007,
+ .EmcPmacroDdllLongCmd_1 = 0x00080008,
+ .EmcPmacroDdllLongCmd_2 = 0x00060006,
+ .EmcPmacroDdllLongCmd_3 = 0x00090009,
+ .EmcPmacroDdllLongCmd_4 = 0x00000007,
+ .EmcPmacroDdllShortCmd_0 = 0x00000000,
+ .EmcPmacroDdllShortCmd_1 = 0x00000000,
+ .EmcPmacroDdllShortCmd_2 = 0x00000000,
+ .WarmBootWait = 0x00000001,
+ .EmcOdtWrite = 0x00000000,
+ .EmcZcalInterval = 0x00064000,
+ .EmcZcalWaitCnt = 0x000900cc,
+ .EmcZcalMrwCmd = 0x0051004f,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000001,
+ .EmcZcalInitDev1 = 0x40000001,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000011,
+ .EmcZqCalLpDdr4WarmBoot = 0x00000001,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x00000000,
+ .EmcWarmBootMrsExtra = 0x00000000,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000001,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x0000000f,
+ .PmcDdrCfg = 0x20120100,
+ .PmcIoDpd3Req = 0x4befffff,
+ .PmcIoDpd3ReqWait = 0x00000001,
+ .PmcIoDpd4ReqWait = 0x00000002,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcDdrCntrlWait = 0x00000000,
+ .PmcDdrCntrl = 0x0007ff8b,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0Byte0 = 0x71245603,
+ .EmcSwizzleRank0Byte1 = 0x16243705,
+ .EmcSwizzleRank0Byte2 = 0x12574630,
+ .EmcSwizzleRank0Byte3 = 0x26147503,
+ .EmcSwizzleRank1Byte0 = 0x71345602,
+ .EmcSwizzleRank1Byte1 = 0x20456713,
+ .EmcSwizzleRank1Byte2 = 0x64071325,
+ .EmcSwizzleRank1Byte3 = 0x54023167,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcDataBrlshft0 = 0x00249249,
+ .EmcDataBrlshft1 = 0x00249249,
+ .EmcDqsBrlshft0 = 0x00000000,
+ .EmcDqsBrlshft1 = 0x00000000,
+ .EmcCmdBrlshft0 = 0x00000000,
+ .EmcCmdBrlshft1 = 0x00000000,
+ .EmcCmdBrlshft2 = 0x00000012,
+ .EmcCmdBrlshft3 = 0x00000012,
+ .EmcQuseBrlshft0 = 0x00000000,
+ .EmcQuseBrlshft1 = 0x00000000,
+ .EmcQuseBrlshft2 = 0x00000000,
+ .EmcQuseBrlshft3 = 0x00000000,
+ .EmcDllCfg0 = 0x1f13412f,
+ .EmcDllCfg1 = 0x00010014,
+ .EmcPmcScratch1 = 0x4befffff,
+ .EmcPmcScratch2 = 0x7fffffff,
+ .EmcPmcScratch3 = 0x4005d70b,
+ .EmcPmacroPadCfgCtrl = 0x00020000,
+ .EmcPmacroVttgenCtrl0 = 0x00030808,
+ .EmcPmacroVttgenCtrl1 = 0x00015000,
+ .EmcPmacroVttgenCtrl2 = 0x00101010,
+ .EmcPmacroBrickCtrlRfu1 = 0x00001600,
+ .EmcPmacroCmdBrickCtrlFdpd = 0x00000000,
+ .EmcPmacroBrickCtrlRfu2 = 0x00000000,
+ .EmcPmacroDataBrickCtrlFdpd = 0x00000000,
+ .EmcPmacroBgBiasCtrl0 = 0x00000030,
+ .EmcPmacroDataPadRxCtrl = 0x10050037,
+ .EmcPmacroCmdPadRxCtrl = 0x00000000,
+ .EmcPmacroDataRxTermMode = 0x00000010,
+ .EmcPmacroCmdRxTermMode = 0x00003000,
+ .EmcPmacroDataPadTxCtrl = 0x02000111,
+ .EmcPmacroCommonPadTxCtrl = 0x00000008,
+ .EmcPmacroCmdPadTxCtrl = 0x0a000000,
+ .EmcCfg3 = 0x00000040,
+ .EmcPmacroTxPwrd0 = 0x10000000,
+ .EmcPmacroTxPwrd1 = 0x08000000,
+ .EmcPmacroTxPwrd2 = 0x10000000,
+ .EmcPmacroTxPwrd3 = 0x08000000,
+ .EmcPmacroTxPwrd4 = 0x00000000,
+ .EmcPmacroTxPwrd5 = 0x00000000,
+ .EmcConfigSampleDelay = 0x00000020,
+ .EmcPmacroBrickMapping0 = 0x28190081,
+ .EmcPmacroBrickMapping1 = 0x44853293,
+ .EmcPmacroBrickMapping2 = 0x76a76a5b,
+ .EmcPmacroTxSelClkSrc0 = 0x00000000,
+ .EmcPmacroTxSelClkSrc1 = 0x00000000,
+ .EmcPmacroTxSelClkSrc2 = 0x00000000,
+ .EmcPmacroTxSelClkSrc3 = 0x00000000,
+ .EmcPmacroTxSelClkSrc4 = 0x00000000,
+ .EmcPmacroTxSelClkSrc5 = 0x00000000,
+ .EmcPmacroDdllBypass = 0xefffefff,
+ .EmcPmacroDdllPwrd0 = 0xc0c0c0c0,
+ .EmcPmacroDdllPwrd1 = 0xc0c0c0c0,
+ .EmcPmacroDdllPwrd2 = 0xdcdcdcdc,
+ .EmcPmacroCmdCtrl0 = 0x0a0a0a0a,
+ .EmcPmacroCmdCtrl1 = 0x0a0a0a0a,
+ .EmcPmacroCmdCtrl2 = 0x0a0a0a0a,
+ .McEmemAdrCfg = 0x00000001,
+ .McEmemAdrCfgDev0 = 0x000d0302,
+ .McEmemAdrCfgDev1 = 0x000d0302,
+ .McEmemAdrCfgChannelMask = 0xffff2400,
+ .McEmemAdrCfgBankMask0 = 0x6e574400,
+ .McEmemAdrCfgBankMask1 = 0x39722800,
+ .McEmemAdrCfgBankMask2 = 0x4b9c1000,
+ .McEmemCfg = 0x00000c00,
+ .McEmemArbCfg = 0x08000001,
+ .McEmemArbOutstandingReq = 0x8000004c,
+ .McEmemArbRefpbHpCtrl = 0x000a1020,
+ .McEmemArbRefpbBankCtrl = 0x80001028,
+ .McEmemArbTimingRcd = 0x00000001,
+ .McEmemArbTimingRp = 0x00000000,
+ .McEmemArbTimingRc = 0x00000003,
+ .McEmemArbTimingRas = 0x00000001,
+ .McEmemArbTimingFaw = 0x00000002,
+ .McEmemArbTimingRrd = 0x00000001,
+ .McEmemArbTimingRap2Pre = 0x00000002,
+ .McEmemArbTimingWap2Pre = 0x00000005,
+ .McEmemArbTimingR2R = 0x00000001,
+ .McEmemArbTimingW2W = 0x00000001,
+ .McEmemArbTimingR2W = 0x00000004,
+ .McEmemArbTimingW2R = 0x00000005,
+ .McEmemArbTimingRFCPB = 0x00000004,
+ .McEmemArbDaTurns = 0x02020000,
+ .McEmemArbDaCovers = 0x00030201,
+ .McEmemArbMisc0 = 0x71c30504,
+ .McEmemArbMisc1 = 0x70000f0f,
+ .McEmemArbMisc2 = 0x00000000,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McDaCfg0 = 0x00000001,
+ .McEmemArbTimingCcdmw = 0x00000008,
+ .McClkenOverride = 0x00008000,
+ .McStatControl = 0x00000000,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac343,
+ .McVideoProtectVprOverride1 = 0x00001ed3,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .McGeneralizedCarveout1Bom = 0x00000000,
+ .McGeneralizedCarveout1BomHi = 0x00000000,
+ .McGeneralizedCarveout1Size128kb = 0x00000008,
+ .McGeneralizedCarveout1Access0 = 0x00000000,
+ .McGeneralizedCarveout1Access1 = 0x00000000,
+ .McGeneralizedCarveout1Access2 = 0x00300000,
+ .McGeneralizedCarveout1Access3 = 0x03000000,
+ .McGeneralizedCarveout1Access4 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout1Cfg0 = 0x04000c75,
+ .McGeneralizedCarveout2Bom = 0x00000000,
+ .McGeneralizedCarveout2BomHi = 0x00000000,
+ .McGeneralizedCarveout2Size128kb = 0x00000002,
+ .McGeneralizedCarveout2Access0 = 0x00000000,
+ .McGeneralizedCarveout2Access1 = 0x00000000,
+ .McGeneralizedCarveout2Access2 = 0x03000000,
+ .McGeneralizedCarveout2Access3 = 0x00000000,
+ .McGeneralizedCarveout2Access4 = 0x00000300,
+ .McGeneralizedCarveout2ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout2Cfg0 = 0x0440167c,
+ .McGeneralizedCarveout3Bom = 0x00000000,
+ .McGeneralizedCarveout3BomHi = 0x00000000,
+ .McGeneralizedCarveout3Size128kb = 0x00000000,
+ .McGeneralizedCarveout3Access0 = 0x00000000,
+ .McGeneralizedCarveout3Access1 = 0x00000000,
+ .McGeneralizedCarveout3Access2 = 0x03000000,
+ .McGeneralizedCarveout3Access3 = 0x00000000,
+ .McGeneralizedCarveout3Access4 = 0x00000300,
+ .McGeneralizedCarveout3ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout3Cfg0 = 0x04401e7c,
+ .McGeneralizedCarveout4Bom = 0x00000000,
+ .McGeneralizedCarveout4BomHi = 0x00000000,
+ .McGeneralizedCarveout4Size128kb = 0x00000008,
+ .McGeneralizedCarveout4Access0 = 0x00000000,
+ .McGeneralizedCarveout4Access1 = 0x00000000,
+ .McGeneralizedCarveout4Access2 = 0x00300000,
+ .McGeneralizedCarveout4Access3 = 0x00000000,
+ .McGeneralizedCarveout4Access4 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout4Cfg0 = 0x04002442,
+ .McGeneralizedCarveout5Bom = 0x00000000,
+ .McGeneralizedCarveout5BomHi = 0x00000000,
+ .McGeneralizedCarveout5Size128kb = 0x00000008,
+ .McGeneralizedCarveout5Access0 = 0x00000000,
+ .McGeneralizedCarveout5Access1 = 0x00000000,
+ .McGeneralizedCarveout5Access2 = 0x00300000,
+ .McGeneralizedCarveout5Access3 = 0x00000000,
+ .McGeneralizedCarveout5Access4 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout5Cfg0 = 0x04002c42,
+ .EmcCaTrainingEnable = 0x00000000,
+ .SwizzleRankByteEncode = 0x0000000e,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0xfff00000,
+ .McMtsCarveoutAdrHi = 0x00000000,
+ .McMtsCarveoutSizeMb = 0x00000000,
+ .McMtsCarveoutRegCtrl = 0x00000000,
+
+},
diff --git a/src/mainboard/google/foster/bct/sdram-unused.inc b/src/mainboard/google/foster/bct/sdram-unused.inc
new file mode 100644
index 0000000000..bef63dcecc
--- /dev/null
+++ b/src/mainboard/google/foster/bct/sdram-unused.inc
@@ -0,0 +1,4 @@
+{ /* dummy. */
+ .MemoryType = NvBootMemoryType_Unused,
+ 0,
+},
diff --git a/src/mainboard/google/foster/bct/spi.cfg b/src/mainboard/google/foster/bct/spi.cfg
new file mode 100644
index 0000000000..2cf9e56da5
--- /dev/null
+++ b/src/mainboard/google/foster/bct/spi.cfg
@@ -0,0 +1,16 @@
+# Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00210001;
+BlockSize = 32768;
+PageSize = 2048;
+PartitionSize = 4194304;
+
+#
+# T210 bct only supports one boot device
+#
+DevType[0] = NvBootDevType_Spi;
+DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
diff --git a/src/mainboard/google/foster/boardid.c b/src/mainboard/google/foster/boardid.c
new file mode 100644
index 0000000000..d5a352ef6b
--- /dev/null
+++ b/src/mainboard/google/foster/boardid.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+
+uint8_t board_id(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/google/foster/bootblock.c b/src/mainboard/google/foster/bootblock.c
new file mode 100644
index 0000000000..e2ad465e6e
--- /dev/null
+++ b/src/mainboard/google/foster/bootblock.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <soc/addressmap.h>
+#include <soc/clk_rst.h>
+#include <soc/clock.h>
+#include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/padconfig.h>
+#include <soc/spi.h> /* FIXME: move back to soc code? */
+
+#include "pmic.h"
+
+static const struct pad_config pmic_pads[] = {
+ PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
+ PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
+};
+
+static const struct pad_config spiflash_pads[] = {
+ /* QSPI fLash: mosi, miso, clk, cs0, hold, wp */
+ PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+ PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+ PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE, QSPI),
+ PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE, QSPI),
+ PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+ PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+};
+
+/********************* TPM ************************************/
+static const struct pad_config tpm_pads[] = {
+ PAD_CFG_SFIO(GEN3_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+ PAD_CFG_SFIO(GEN3_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+};
+
+static const struct funit_cfg funits[] = {
+ /* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
+ FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
+ /* SPI flash at 24MHz on QSPI controller. */
+ FUNIT_CFG(QSPI, PLLP, 24000, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
+ /* Foster has no TPM yet. This is for futurn TPM on I2C3 @ 400kHz. */
+ FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
+};
+
+static const struct pad_config uart_console_pads[] = {
+ /* UARTA: tx, rx, rts, cts */
+ PAD_CFG_SFIO(UART1_TX, PINMUX_PULL_NONE, UARTA),
+ PAD_CFG_SFIO(UART1_RX, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UARTA),
+ PAD_CFG_SFIO(UART1_RTS, PINMUX_PULL_UP, UARTA),
+ PAD_CFG_SFIO(UART1_CTS, PINMUX_PULL_UP, UARTA),
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
+}
+
+static void set_clock_sources(void)
+{
+ /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
+ write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
+}
+
+void bootblock_mainboard_init(void)
+{
+ set_clock_sources();
+
+ soc_configure_funits(funits, ARRAY_SIZE(funits));
+
+ i2c_init(I2CPWR_BUS);
+ pmic_init(I2CPWR_BUS);
+
+ /* Foster has no TPM yet. This is for future TPM. */
+ i2c_init(I2C3_BUS);
+}
diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c
new file mode 100644
index 0000000000..83dd65268b
--- /dev/null
+++ b/src/mainboard/google/foster/chromeos.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <gpio.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ int count = 0;
+
+ /* TBD(twarren@nvidia.com): Any analogs for these on Foster-FFD? */
+
+ /* Write Protect: active low */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = get_write_protect_state();
+ strncpy((char *)gpios->gpios[count].name, "write protect",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Recovery: active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "recovery",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* TODO: Power: active low / high depending on board id */
+ gpios->gpios[count].port = GPIO(X5);
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "power",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Developer: virtual GPIO active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "developer",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* TODO: Reset: active low (output) */
+ gpios->gpios[count].port = GPIO(I5);
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "reset",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+ gpios->count = count;
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ uint32_t ec_events;
+
+ ec_events = google_chromeec_get_events_b();
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+#else
+ return 0;
+#endif
+}
+
+int get_write_protect_state(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/google/foster/devicetree.cb b/src/mainboard/google/foster/devicetree.cb
new file mode 100644
index 0000000000..947a26987a
--- /dev/null
+++ b/src/mainboard/google/foster/devicetree.cb
@@ -0,0 +1,95 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+chip soc/nvidia/tegra210
+ register "spintable_addr" = "0x80000008"
+
+ device cpu_cluster 0 on
+ device cpu 0 on end
+ device cpu 1 on end
+ device cpu 2 on end
+ device cpu 3 on end
+ end
+
+ register "display_controller" = "TEGRA_ARM_DISPLAYA"
+ register "xres" = "1366"
+ register "yres" = "768"
+
+ # framebuffer resolution
+ register "display_xres" = "1368"
+ register "display_yres" = "678"
+
+ # bits per pixel and color depth
+ register "framebuffer_bits_per_pixel" = "16"
+ register "color_depth" = "6"
+
+ register "panel_bits_per_pixel" = "18"
+
+# How to compute these: xrandr --verbose will give you this:
+#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
+# 2560 2608 2640 2720 hborder 0
+# 1700 1703 1713 1749 vborder 0
+#Then you can compute your values:
+#H front porch = 2608 - 2560 = 48
+#H sync = 2640 - 2608 = 32
+#H back porch = 2720 - 2640 = 80
+#V front porch = 1703 - 1700 = 3
+#V sync = 1713 - 1703 = 10
+#V back porch = 1749 - 1713 = 36
+#href_to_sync and vref_to_sync are from the vendor
+#this is just an example for a Pixel panel; other panels differ.
+# Here is a peppy panel:
+# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
+# h: width 1366 start 1502 end 1532 total 1592
+# v: height 768 start 776 end 788 total 800
+ register "href_to_sync" = "1"
+ register "hfront_porch" = "136"
+ register "hsync_width" = "30"
+ register "hback_porch" = "60"
+
+ register "vref_to_sync" = "1"
+ register "vfront_porch" = "8"
+ register "vsync_width" = "12"
+ register "vback_porch" = "12"
+
+ register "pixel_clock" = "76400000"
+
+ register "win_opt" = "SOR_ENABLE"
+
+ #
+ # dp specific fields
+ #
+ register "dp.pwm" = "1"
+
+ # various panel delay time
+ register "dp.vdd_to_hpd_delay_ms" = "200"
+ register "dp.hpd_unplug_min_us" = "2000"
+ register "dp.hpd_plug_min_us" = "250"
+ register "dp.hpd_irq_min_us" = "250"
+
+ # link configurations
+ register "dp.lane_count" = "1"
+ register "dp.enhanced_framing" = "1"
+ register "dp.link_bw" = "10"
+ # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
+
+ register "dp.drive_current" = "0x40404040"
+ register "dp.preemphasis" = "0x0f0f0f0f"
+ register "dp.postcursor" = "0"
+end
diff --git a/src/mainboard/google/foster/ec_dummy.c b/src/mainboard/google/foster/ec_dummy.c
new file mode 100644
index 0000000000..01a935c79f
--- /dev/null
+++ b/src/mainboard/google/foster/ec_dummy.c
@@ -0,0 +1,9 @@
+/* Dummy CHROMEEC file to provide stub functions for vboot compilation */
+
+#include <stdint.h>
+
+int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len);
+int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
+{
+ return 0;
+}
diff --git a/src/mainboard/google/foster/mainboard.c b/src/mainboard/google/foster/mainboard.c
new file mode 100644
index 0000000000..3f4e10fc65
--- /dev/null
+++ b/src/mainboard/google/foster/mainboard.c
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <arch/mmu.h>
+#include <boot/coreboot_tables.h>
+#include <delay.h>
+#include <device/device.h>
+#include <memrange.h>
+#include <soc/addressmap.h>
+#include <soc/clk_rst.h>
+#include <soc/clock.h>
+#include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/padconfig.h>
+#include <soc/spi.h>
+#include <soc/nvidia/tegra/dc.h>
+#include <soc/display.h>
+
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static const struct pad_config sdmmc1_pad[] = {
+ /* MMC1(SDCARD) */
+ PAD_CFG_SFIO(SDMMC1_CLK, PINMUX_INPUT_ENABLE, SDMMC1),
+ PAD_CFG_SFIO(SDMMC1_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
+ PAD_CFG_SFIO(SDMMC1_DAT0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
+ PAD_CFG_SFIO(SDMMC1_DAT1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
+ PAD_CFG_SFIO(SDMMC1_DAT2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
+ PAD_CFG_SFIO(SDMMC1_DAT3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC1),
+ /* MMC1 Card Detect pin */
+ PAD_CFG_GPIO_INPUT(GPIO_PZ1, PINMUX_PULL_UP),
+ /* Disable SD card reader power so it can be reset even on warm boot.
+ Payloads must enable power before accessing SD card slots. */
+ PAD_CFG_GPIO_OUT0(GPIO_PZ4, PINMUX_PULL_NONE),
+};
+
+static const struct pad_config audio_codec_pads[] = {
+ /* GPIO_X1_AUD(BB3) is AUDIO_LDO_EN (->CODEC RESET_N pin) */
+ PAD_CFG_GPIO_OUT1(GPIO_X1_AUD, PINMUX_PULL_DOWN),
+};
+
+static const struct pad_config padcfgs[] = {
+ /* We pull the USB VBUS signals up but keep them as inputs since the
+ * voltage source likes to drive them low on overcurrent conditions */
+ PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_NONE | PINMUX_PARKED |
+ PINMUX_INPUT_ENABLE | PINMUX_LPDR | PINMUX_IO_HV),
+
+ /* Add backlight vdd/enable/pwm/dp hpd pad cfgs here */
+};
+
+static const struct pad_config i2c1_pad[] = {
+ /* GEN1 I2C */
+ PAD_CFG_SFIO(GEN1_I2C_SCL, PINMUX_INPUT_ENABLE, I2C1),
+ PAD_CFG_SFIO(GEN1_I2C_SDA, PINMUX_INPUT_ENABLE, I2C1),
+};
+
+static const struct pad_config i2s1_pad[] = {
+ /* I2S1 */
+ PAD_CFG_SFIO(DAP1_SCLK, PINMUX_INPUT_ENABLE, I2S1),
+ PAD_CFG_SFIO(DAP1_FS, PINMUX_INPUT_ENABLE, I2S1),
+ PAD_CFG_SFIO(DAP1_DOUT, PINMUX_INPUT_ENABLE, I2S1),
+ PAD_CFG_SFIO(DAP1_DIN, PINMUX_INPUT_ENABLE | PINMUX_TRISTATE, I2S1),
+ /* codec MCLK via AUD SFIO */
+ PAD_CFG_SFIO(AUD_MCLK, PINMUX_PULL_NONE, AUD),
+};
+
+static const struct funit_cfg audio_funit[] = {
+ /* We need 1.5MHz for I2S1. So we use CLK_M */
+ FUNIT_CFG(I2S1, CLK_M, 1500, i2s1_pad, ARRAY_SIZE(i2s1_pad)),
+};
+
+static const struct funit_cfg funitcfgs[] = {
+ FUNIT_CFG(SDMMC1, PLLP, 48000, sdmmc1_pad, ARRAY_SIZE(sdmmc1_pad)),
+ FUNIT_CFG(SDMMC4, PLLP, 48000, NULL, 0),
+ FUNIT_CFG(I2C1, PLLP, 100, i2c1_pad, ARRAY_SIZE(i2c1_pad)),
+ FUNIT_CFG_USB(USBD),
+};
+
+/* Audio init: clocks and enables/resets */
+static void setup_audio(void)
+{
+ /* Audio codec (ES755) uses OSC freq (via AUD_MCLK), s/b 38.4MHz */
+ soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
+
+ /*
+ * As per NVIDIA hardware team, we need to take ALL audio devices
+ * connected to AHUB (AUDIO, APB2APE, I2S, SPDIF, etc.) out of reset
+ * and clock-enabled, otherwise reading AHUB devices (in our case,
+ * I2S/APBIF/AUDIO<XBAR>) will hang.
+ */
+ soc_configure_ape();
+ clock_enable_audio();
+}
+
+static void mainboard_init(device_t dev)
+{
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+ soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
+
+ i2c_init(I2C1_BUS);
+ setup_audio();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "foster",
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/foster/memlayout.ld b/src/mainboard/google/foster/memlayout.ld
new file mode 100644
index 0000000000..a71dcb8508
--- /dev/null
+++ b/src/mainboard/google/foster/memlayout.ld
@@ -0,0 +1,6 @@
+#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
+#include <soc/memlayout_vboot2.ld>
+#else
+#include <soc/memlayout.ld>
+#endif
+
diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c
new file mode 100644
index 0000000000..b549107059
--- /dev/null
+++ b/src/mainboard/google/foster/pmic.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "pmic.h"
+#include "reset.h"
+
+enum {
+ MAX77620_I2C_ADDR = 0x3c
+};
+
+struct max77620_init_reg {
+ u8 reg;
+ u8 val;
+ u8 delay;
+};
+
+static struct max77620_init_reg init_list[] = {
+ /* TODO */
+};
+
+static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
+{
+ if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) {
+ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
+ __func__, reg, val);
+ /* Reset the SoC on any PMIC write error */
+ cpu_reset();
+ } else {
+ if (delay)
+ udelay(500);
+ }
+}
+
+static void pmic_slam_defaults(unsigned bus)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(init_list); i++) {
+ struct max77620_init_reg *reg = &init_list[i];
+ pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
+ }
+}
+
+void pmic_init(unsigned bus)
+{
+ /* Restore PMIC POR defaults, in case kernel changed 'em */
+ pmic_slam_defaults(bus);
+
+ /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
+ pmic_write_reg(bus, MAX77620_GPIO5_REG, 0x09, 1);
+
+ /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN -- ??? */
+ pmic_write_reg(bus, MAX77620_GPIO1_REG, 0x09, 1);
+
+ /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
+ pmic_write_reg(bus, MAX77620_AME_GPIO, 0x1c, 1);
+
+ /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v? */
+ pmic_write_reg(bus, MAX77620_CNFG2SD_REG, 0x04, 1);
+
+ pmic_write_reg(bus, MAX77620_SD1_REG, 0x2a, 1);
+
+ /* CNFG1_L2 = 0xF2 for 3.3v, enabled */
+ pmic_write_reg(bus, MAX77620_CNFG1_L2_REG, 0xf2, 1);
+
+ /* CNFG1_L1 = 0xCA for 1.05v, enabled */
+ pmic_write_reg(bus, MAX77620_CNFG1_L1_REG, 0xca, 1);
+
+ printk(BIOS_DEBUG, "PMIC init done\n");
+}
diff --git a/src/mainboard/google/foster/pmic.h b/src/mainboard/google/foster/pmic.h
new file mode 100644
index 0000000000..a2556f5f54
--- /dev/null
+++ b/src/mainboard/google/foster/pmic.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
+#define __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
+
+#define MAX77620_SD0_REG 0x16
+#define MAX77620_SD1_REG 0x17
+#define MAX77620_SD2_REG 0x18
+#define MAX77620_SD3_REG 0x19
+#define MAX77620_CNFG2SD_REG 0x22
+
+#define MAX77620_CNFG1_L0_REG 0x23
+#define MAX77620_CNFG2_L0_REG 0x24
+#define MAX77620_CNFG1_L1_REG 0x25
+#define MAX77620_CNFG2_L1_REG 0x26
+#define MAX77620_CNFG1_L2_REG 0x27
+#define MAX77620_CNFG2_L2_REG 0x28
+#define MAX77620_CNFG1_L3_REG 0x29
+#define MAX77620_CNFG2_L3_REG 0x2A
+#define MAX77620_CNFG1_L4_REG 0x2B
+#define MAX77620_CNFG2_L4_REG 0x2C
+#define MAX77620_CNFG1_L5_REG 0x2D
+#define MAX77620_CNFG2_L5_REG 0x2E
+#define MAX77620_CNFG1_L6_REG 0x2F
+#define MAX77620_CNFG2_L6_REG 0x30
+#define MAX77620_CNFG1_L7_REG 0x31
+#define MAX77620_CNFG2_L7_REG 0x32
+#define MAX77620_CNFG1_L8_REG 0x33
+#define MAX77620_CNFG2_L8_REG 0x34
+#define MAX77620_CNFG3_LDO_REG 0x35
+
+#define MAX77620_GPIO0_REG 0x36
+#define MAX77620_GPIO1_REG 0x37
+#define MAX77620_GPIO2_REG 0x38
+#define MAX77620_GPIO3_REG 0x39
+#define MAX77620_GPIO4_REG 0x3A
+#define MAX77620_GPIO5_REG 0x3B
+#define MAX77620_GPIO6_REG 0x3C
+#define MAX77620_GPIO7_REG 0x3D
+#define MAX77620_GPIO_PUE_GPIO 0x3E
+#define MAX77620_GPIO_PDE_GPIO 0x3F
+
+#define MAX77620_AME_GPIO 0x40
+#define MAX77620_REG_ONOFF_CFG1 0x41
+#define MAX77620_REG_ONOFF_CFG2 0x42
+
+#define MAX77620_CID0_REG 0x58
+#define MAX77620_CID1_REG 0x59
+#define MAX77620_CID2_REG 0x5A
+#define MAX77620_CID3_REG 0x5B
+#define MAX77620_CID4_REG 0x5C
+#define MAX77620_CID5_REG 0x5D
+
+void pmic_init(unsigned bus);
+
+#endif /* __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ */
diff --git a/src/mainboard/google/foster/reset.c b/src/mainboard/google/foster/reset.c
new file mode 100644
index 0000000000..0c44a641a1
--- /dev/null
+++ b/src/mainboard/google/foster/reset.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <gpio.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+ gpio_output(GPIO(I5), 0);
+ while(1);
+}
diff --git a/src/mainboard/google/foster/romstage.c b/src/mainboard/google/foster/romstage.c
new file mode 100644
index 0000000000..178ac10424
--- /dev/null
+++ b/src/mainboard/google/foster/romstage.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/padconfig.h>
+#include <soc/romstage.h>
+
+void romstage_mainboard_init(void)
+{
+ /* No EC or TPM on Foster, do nothing here */
+}
+
+void mainboard_configure_pmc(void)
+{
+}
+
+void mainboard_enable_vdd_cpu(void)
+{
+ /* VDD_CPU is already enabled in bootblock. */
+}
diff --git a/src/mainboard/google/foster/verstage.c b/src/mainboard/google/foster/verstage.c
new file mode 100644
index 0000000000..d5bcd44680
--- /dev/null
+++ b/src/mainboard/google/foster/verstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/funitcfg.h>
+#include <soc/padconfig.h>
+#include <soc/verstage.h>
+#include <soc/nvidia/tegra/i2c.h>
+
+void verstage_mainboard_init(void)
+{
+}