diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-10-09 09:23:33 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:16:38 +0100 |
| commit | 4a6ac1e0e7fb07338cb25ab081aaace4aca70ad8 (patch) | |
| tree | dce2c2e6baadb4fabff6b8e1daeb403e143e4395 /src/mainboard/google/glados/devicetree.cb | |
| parent | a9ba45955018357cb1df57ba46c138929e564d76 (diff) | |
| download | coreboot-4a6ac1e0e7fb07338cb25ab081aaace4aca70ad8.tar.xz | |
google/glados: Add USB phy settings and update enabled options
- Add placeholder USB phy settings, needs tuning still
- Change UART2 to be skipped during FSP init
- Update headphone codec irq to be level triggered as
that is how the kernel is configuring it
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I9a15a27dab49d4e19f8ef0574ee2e61ae90c99fc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e7a0032ba23d6762342639c2c7cb877c1f90452
Original-Change-Id: Ie1439f21116022b0644d06853df9490e4651a9ae
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304926
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/glados/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index e57c4906ef..797865ddc8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -65,6 +65,43 @@ chip soc/intel/skylake register "PortUsb30Enable[2]" = "1" # Type-A Port 1 register "PortUsb30Enable[3]" = "1" # Type-A Port 2 + # USB Per Port HS Preemphasis Bias + register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \ + 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \ + 0x07, 0x07, 0x07, 0x07 }" + + # USB Per Port HS Transmitter Bias + register "Usb2AfeTxiset" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00 }" + + # USB Per Port HS Transmitter Emphasis + register "Usb2AfePredeemp" = "{ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, \ + 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, \ + 0x03, 0x03, 0x03, 0x03 }" + + # USB Per Port Half Bit Pre-emphasis + register "Usb2AfePehalfbit" = "{ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, \ + 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00 }" + + # Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + register "Usb3HsioTxDeEmphEnable" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00 }" + + # USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + register "Usb3HsioTxDeEmph" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00 }" + + # Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + register "Usb3HsioTxDownscaleAmpEnable" = "{ 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00 }" + + # USB 3.0 TX Output Downscale Amplitude Adjustment + register "Usb3HsioTxDownscaleAmp" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00 }" + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ @@ -77,7 +114,7 @@ chip soc/intel/skylake [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoPci, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" device cpu_cluster 0 on |