diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-17 09:53:22 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-27 14:19:09 +0000 |
| commit | 56260850e8274d6088cbddca2e06a8735aa22995 (patch) | |
| tree | c881e4be41b91da4ec812c8161d1e038fea9d951 /src/mainboard/google/glados/gpio.h | |
| parent | c3281917289bbc2cb39f62c46418053b57fa33e3 (diff) | |
| download | coreboot-56260850e8274d6088cbddca2e06a8735aa22995.tar.xz | |
glados: Abstract board GPIO configuration in gpio.h
Move all the various places that look at board specific GPIOs into
the mainboard gpio.h so it can be easily ported to new boards.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293942
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11282
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/glados/gpio.h')
| -rw-r--r-- | src/mainboard/google/glados/gpio.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index c7cd5ae0c5..fc5ffffbac 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -20,8 +20,31 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include <soc/gpe.h> #include <soc/gpio.h> +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), @@ -193,5 +216,6 @@ static const struct pad_config gpio_table[] = { /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* LANPHYC */ /* GPD11 */ }; +#endif #endif |