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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-09 21:02:36 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-21 14:23:21 +0000 |
| commit | f89cb241eecdf70d9e52c852833c6ed1e3b9632d (patch) | |
| tree | 3f8ab425bf8a78f517c17f41598e0c60a390c18b /src/mainboard/google/glados/ramstage.c | |
| parent | 24ba85002a5eb49c501888338a84308835b340ab (diff) | |
| download | coreboot-f89cb241eecdf70d9e52c852833c6ed1e3b9632d.tar.xz | |
mb/google/glados: port to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados/ramstage.c')
| -rw-r--r-- | src/mainboard/google/glados/ramstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c index 27d674d713..15912cf862 100644 --- a/src/mainboard/google/glados/ramstage.c +++ b/src/mainboard/google/glados/ramstage.c @@ -17,7 +17,7 @@ #include <soc/ramstage.h> #include <variant/gpio.h> -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ |