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author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-09 21:02:36 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-21 14:23:21 +0000 |
commit | f89cb241eecdf70d9e52c852833c6ed1e3b9632d (patch) | |
tree | 3f8ab425bf8a78f517c17f41598e0c60a390c18b /src/mainboard/google/glados/romstage.c | |
parent | 24ba85002a5eb49c501888338a84308835b340ab (diff) | |
download | coreboot-f89cb241eecdf70d9e52c852833c6ed1e3b9632d.tar.xz |
mb/google/glados: port to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados/romstage.c')
-rw-r--r-- | src/mainboard/google/glados/romstage.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index f2daa38d00..113d28bd50 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -25,18 +25,18 @@ #include "spd/spd_util.h" #include "spd/spd.h" -void mainboard_pre_raminit(struct romstage_params *params) + +void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT /* Turn on keyboard backlight to indicate we are booting */ - if (params->power_state->prev_sleep_state != ACPI_S3) + const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME) google_chromeec_kbbacklight(25); #endif -} -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ /* Get SPD index */ const gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, @@ -46,9 +46,9 @@ void mainboard_memory_init_params(struct romstage_params *params, }; const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - memory_params->MemorySpdDataLen = SPD_LEN; - memory_params->DqPinsInterleaved = FALSE; + mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->DqPinsInterleaved = FALSE; - spd_memory_init_params(memory_params, spd_idx); - variant_memory_init_params(memory_params, spd_idx); + spd_memory_init_params(mupd, spd_idx); + variant_memory_init_params(mupd, spd_idx); } |