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authorDuncan Laurie <dlaurie@chromium.org>2015-07-22 09:21:29 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-07-24 15:35:15 +0200
commitd8d686663c3a9bd8cbcfb2b7a0d81ce4af678779 (patch)
tree885428533ca7a3333d5069ad911d6cc7c54f123b /src/mainboard/google/glados/spd
parent31be8e403f65a3e086168bf088355ba71368531c (diff)
downloadcoreboot-d8d686663c3a9bd8cbcfb2b7a0d81ce4af678779.tar.xz
glados: Support reading memory strap GPIOs to select SPD
Add some board specific code to enable the memory configuration GPIOs in GPIO input mode and read them to determine which memory type is on the board. Also add the other memory types that are not yet present in the glados mainboard directory. This should be replaced with the real gpio infrastructure once it is ready. BUG=chrome-os-partner:43069 BRANCH=none TEST=build and boot on glados Change-Id: I7a9ce10e92ad6681528572e87b6cfee29880841a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d81e969c5950fd89bb745d1403abddb08a942f83 Original-Change-Id: Iffb0bd5c176f2adbdd9302d9bff5b7bde725d671 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287436 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados/spd')
-rw-r--r--src/mainboard/google/glados/spd/Makefile.inc6
-rw-r--r--src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex16
-rw-r--r--src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex16
-rw-r--r--src/mainboard/google/glados/spd/spd.c44
4 files changed, 75 insertions, 7 deletions
diff --git a/src/mainboard/google/glados/spd/Makefile.inc b/src/mainboard/google/glados/spd/Makefile.inc
index d8c0c51109..f415ef81ec 100644
--- a/src/mainboard/google/glados/spd/Makefile.inc
+++ b/src/mainboard/google/glados/spd/Makefile.inc
@@ -23,8 +23,10 @@ romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# SPD data by index. No method for board identification yet
-SPD_SOURCES = samsung_dimm_K4E6E304EE-EGCF # 0
-SPD_SOURCES += empty # 1
+SPD_SOURCES = empty # 0b0000
+SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001
+SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR # 0b0010
+SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR # 0b0011
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
new file mode 100644
index 0000000000..f724c748f8
--- /dev/null
+++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
+54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex
new file mode 100644
index 0000000000..c3a3888978
--- /dev/null
+++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
+54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c
index 5ee12f5f57..1882fa7494 100644
--- a/src/mainboard/google/glados/spd/spd.c
+++ b/src/mainboard/google/glados/spd/spd.c
@@ -24,6 +24,7 @@
#include <string.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
+#include <soc/pcr.h>
#include <soc/romstage.h>
#include "spd.h"
@@ -84,6 +85,42 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
char *spd_file;
size_t spd_file_len;
int spd_index;
+ int spd_gpio[4];
+
+ /*************************************************************
+ * FIXME: Remove when real GPIO support is ready.
+ */
+ GPIO_PAD gpio_set[4] = {
+ GPIO_LP_GPP_C12, /* PCH_MEM_CONFIG[0] */
+ GPIO_LP_GPP_C13, /* PCH_MEM_CONFIG[1] */
+ GPIO_LP_GPP_C14, /* PCH_MEM_CONFIG[2] */
+ GPIO_LP_GPP_C15, /* PCH_MEM_CONFIG[3] */
+ };
+ int index;
+
+ for (index = 0; index < ARRAY_SIZE(gpio_set); index++) {
+ u32 number = GPIO_GET_PAD_NUMBER(gpio_set[index]);
+ u32 cfgreg = 8 * number + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET;
+ /*
+ * Set GPIO mode and enable input
+ * Clear PMODE0 | PMODE1 | GPIORXDIS
+ */
+ u32 dw0mask = (1 << 10) | (1 << 11) | (1 << 9);
+ u32 dw0reg = 0;
+ pcr_andthenor32(PID_GPIOCOM1, cfgreg, ~dw0mask, dw0reg);
+
+ /* Read current input value */
+ pcr_read32(PID_GPIOCOM1, cfgreg, &dw0reg);
+ spd_gpio[index] = !!(dw0reg & (1 << 1));
+ }
+ /*************************************************************/
+
+ spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) |
+ (spd_gpio[1] << 1) | spd_gpio[0];
+
+ printk(BIOS_DEBUG,
+ "SPD: index %d (GPP_C15=%d GPP_C14=%d GPP_C13=%d GPP_C12=%d)\n",
+ spd_index, spd_gpio[3], spd_gpio[2], spd_gpio[1], spd_gpio[0]);
/* Load SPD data from CBFS */
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
@@ -95,13 +132,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
if (spd_file_len < SPD_LEN)
die("Missing SPD data.");
- /* Add board SKU detection here. Currently we only support one. */
- spd_index = 0;
-
/* Make sure we did not overrun the buffer */
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
+ printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
+ spd_index = 1;
}
/* Assume same memory in both channels */