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| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-31 12:18:44 -0500 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2020-04-03 16:23:10 +0000 |
| commit | d957d12e6dbf2eb912904f8cda7f9138a2ac314e (patch) | |
| tree | 303eeb7c41cf0f5af26367f01e36a9c7c9eb3ee6 /src/mainboard/google/glados/variants/cave/devicetree.cb | |
| parent | e4c784bd0d91fe0bf4e0e8e5b0c9fa173235cea6 (diff) | |
| download | coreboot-d957d12e6dbf2eb912904f8cda7f9138a2ac314e.tar.xz | |
mb/google/glados: clean up variant devicetrees
In preparation for conversion to overridetree format, clean up
the variant devicetrees in order to minimize the differences
across glados variants. This entails:
- minor reformatting and reordering of devicetree entries
- addition of setting default values on boards which skipped them
- disabling unused I2C2 on boards which left it enabled
- ensuring TCC offset set for all SKL-Y boards
- setting VR mailbox command 1 for caroline
- skipping init for UART2 on cave and glados
- dropping unused PCIe RP5 for sentry
Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados/variants/cave/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/glados/variants/cave/devicetree.cb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 1d04a8e714..41bb82e053 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -167,7 +167,7 @@ chip soc/intel/skylake [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # I2C4 is 1.8V @@ -176,11 +176,12 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15" - register "tcc_offset" = "10" # TCC of 90C - # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # TCC of 90C + register "tcc_offset" = "10" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" |