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authorAngel Pons <th3fanbus@gmail.com>2020-07-25 11:27:49 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-26 20:54:32 +0000
commita634dab1a66d47023a16eaa1ec0a6f0eec688ef0 (patch)
tree479b6bc5213f3d7477e03a97170de004791917f9 /src/mainboard/google/glados
parentd8f44360054b6f63d4cf76be179c4d1193e456ae (diff)
downloadcoreboot-a634dab1a66d47023a16eaa1ec0a6f0eec688ef0.tar.xz
skylake boards: Factor out copy-pasted PIRQ routes
Put them in common code just in case something depends on the values. Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados')
-rw-r--r--src/mainboard/google/glados/devicetree.cb9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index f7be80d460..84e9693ed4 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -64,15 +64,6 @@ chip soc/intel/skylake
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "pirqa_routing" = "PCH_IRQ11"
- register "pirqb_routing" = "PCH_IRQ10"
- register "pirqc_routing" = "PCH_IRQ11"
- register "pirqd_routing" = "PCH_IRQ11"
- register "pirqe_routing" = "PCH_IRQ11"
- register "pirqf_routing" = "PCH_IRQ11"
- register "pirqg_routing" = "PCH_IRQ11"
- register "pirqh_routing" = "PCH_IRQ11"
-
# Enable Root port 1
register "PcieRpEnable[0]" = "1"
# Enable CLKREQ#