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authorAaron Durbin <adurbin@chromium.org>2015-08-20 12:18:08 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-08-29 07:22:03 +0000
commit31718c039f70c2903623e679bcb56a88bf5937ed (patch)
tree5a9bdee4bf6571a3d4cbf14e85e4f7192bbaa8e6 /src/mainboard/google/glados
parenta58cf01a1fd545c01b036f9abaf354440822f043 (diff)
downloadcoreboot-31718c039f70c2903623e679bcb56a88bf5937ed.tar.xz
google/glados: fix kepler probing
On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/glados')
-rw-r--r--src/mainboard/google/glados/gpio.h8
-rw-r--r--src/mainboard/google/glados/romstage.c11
2 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index c4d3d920d8..fb37b3bcf8 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -48,6 +48,7 @@
#define EC_SMI_GPI GPP_E15
#ifndef __ACPI__
+/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
@@ -219,6 +220,13 @@ static const struct pad_config gpio_table[] = {
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* LANPHYC */ /* GPD11 */
};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+};
+
#endif
#endif
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index 4d9aaf4208..36a8453ed7 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -27,10 +27,21 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
+#include "gpio.h"
#include "spd/spd.h"
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't be. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
void mainboard_romstage_entry(struct romstage_params *params)
{
+ early_config_gpio();
+
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);