summaryrefslogtreecommitdiff
path: root/src/mainboard/google/glados
diff options
context:
space:
mode:
authorMatt DeVillier <matt.devillier@gmail.com>2018-07-07 19:03:06 -0500
committerMartin Roth <martinroth@google.com>2018-07-21 00:49:52 +0000
commit357ea55f454a77dd5c2a9b14e5d7d5946b433146 (patch)
treed4440490f46869dddaeb620ecf975eef89869e54 /src/mainboard/google/glados
parent39f3c7e1840823c294d7cedf11aed62bdd765141 (diff)
downloadcoreboot-357ea55f454a77dd5c2a9b14e5d7d5946b433146.tar.xz
google/lars: Convert to a variant of glados
Convert lars to a variant of glados Skylake reference board: - add lars-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add conditional generation of NHLT ACPI data for Maxim codec, including override of OEM ID and OEM table ID - remove existing lars board/directory Test: build/boot google/lars, verify functionality unchanged from pre-variant configuration Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27413 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados')
-rw-r--r--src/mainboard/google/glados/Kconfig6
-rw-r--r--src/mainboard/google/glados/Kconfig.name7
-rw-r--r--src/mainboard/google/glados/mainboard.c17
-rw-r--r--src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex16
-rw-r--r--src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex16
-rw-r--r--src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex16
-rw-r--r--src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex16
-rw-r--r--src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex16
-rw-r--r--src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex16
-rw-r--r--src/mainboard/google/glados/variants/lars/Makefile.inc51
-rw-r--r--src/mainboard/google/glados/variants/lars/board_info.txt6
-rw-r--r--src/mainboard/google/glados/variants/lars/data.vbtbin0 -> 4608 bytes
-rw-r--r--src/mainboard/google/glados/variants/lars/devicetree.cb286
-rw-r--r--src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl134
-rw-r--r--src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl0
-rw-r--r--src/mainboard/google/glados/variants/lars/include/variant/ec.h20
-rw-r--r--src/mainboard/google/glados/variants/lars/include/variant/gpio.h234
-rw-r--r--src/mainboard/google/glados/variants/lars/variant.c78
18 files changed, 934 insertions, 1 deletions
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 9ef8736dc2..99e538f5df 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -38,6 +38,7 @@ config MAINBOARD_PART_NUMBER
string
default "Chell" if BOARD_GOOGLE_CHELL
default "Glados" if BOARD_GOOGLE_GLADOS
+ default "Lars" if BOARD_GOOGLE_LARS
config MAINBOARD_FAMILY
string
@@ -47,11 +48,13 @@ config VARIANT_DIR
string
default "chell" if BOARD_GOOGLE_CHELL
default "glados" if BOARD_GOOGLE_GLADOS
+ default "lars" if BOARD_GOOGLE_LARS
config DEVICETREE
string
default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL
default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
+ default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS
config MAX_CPUS
int
@@ -70,15 +73,18 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME
string
default "chell" if BOARD_GOOGLE_CHELL
default "glados" if BOARD_GOOGLE_GLADOS
+ default ""
config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
string
default "chell_pd" if BOARD_GOOGLE_CHELL
default "glados_pd" if BOARD_GOOGLE_GLADOS
+ default ""
config GBB_HWID
string
depends on CHROMEOS
default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
+ default "LARS TEST 5001" if BOARD_GOOGLE_LARS
endif
diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name
index 1f2365437b..074d9c35d6 100644
--- a/src/mainboard/google/glados/Kconfig.name
+++ b/src/mainboard/google/glados/Kconfig.name
@@ -10,3 +10,10 @@ config BOARD_GOOGLE_GLADOS
select BOARD_GOOGLE_BASEBOARD_GLADOS
select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS
select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS
+
+config BOARD_GOOGLE_LARS
+ bool "-> Lars (Acer Chromebook 14 for Work (CP5-471))"
+ select BOARD_GOOGLE_BASEBOARD_GLADOS
+ select DRIVERS_GENERIC_MAX98357A
+ select EXCLUDE_NATIVE_SD_INTERFACE
+ select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
index 921595edd6..451b3d4336 100644
--- a/src/mainboard/google/glados/mainboard.c
+++ b/src/mainboard/google/glados/mainboard.c
@@ -24,6 +24,9 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
+static const char *oem_id_maxim = "INTEL";
+static const char *oem_table_id_maxim = "SCRDMAX";
+
static void mainboard_init(struct device *dev)
{
mainboard_ec_init();
@@ -35,6 +38,8 @@ static unsigned long mainboard_write_acpi_tables(
uintptr_t start_addr;
uintptr_t end_addr;
struct nhlt *nhlt;
+ const char *oem_id = NULL;
+ const char *oem_table_id = NULL;
start_addr = current;
@@ -57,11 +62,21 @@ static unsigned long mainboard_write_acpi_tables(
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add ssm4567.\n");
+ /* MAXIM Smart Amps for left and right. */
+ if (IS_ENABLED(CONFIG_NHLT_MAX98357)) {
+ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
+ printk(BIOS_ERR, "Couldn't add max98357.\n");
+
+ oem_id = oem_id_maxim;
+ oem_table_id = oem_table_id_maxim;
+ }
+
/* NAU88l25 Headset codec. */
if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
printk(BIOS_ERR, "Couldn't add headset codec.\n");
- end_addr = nhlt_soc_serialize(nhlt, start_addr);
+ end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
+ oem_id, oem_table_id, 0);
if (end_addr != start_addr)
acpi_add_table(rsdp, (void *)start_addr);
diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
new file mode 100644
index 0000000000..529b775c71
--- /dev/null
+++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00
+48 39 43 43 4E 4E 4E 38 4A 54 42 4C 41 52 2D 4E
+55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file
diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
new file mode 100644
index 0000000000..62a37bd0d0
--- /dev/null
+++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4C 54 42 4C 41 52 2D 4E
+55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file
diff --git a/src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex b/src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
new file mode 100644
index 0000000000..8694a407f9
--- /dev/null
+++ b/src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 03 03 11 01 08 09 00 00 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 10 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 75 8C
+4D 54 35 32 4C 32 35 36 4D 33 32 44 31 50 46 31
+30 37 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex b/src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
new file mode 100644
index 0000000000..b0593759e5
--- /dev/null
+++ b/src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 21 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 3D 51
+4D 54 35 32 4C 35 31 32 4D 33 32 44 32 50 46 31
+30 37 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
new file mode 100644
index 0000000000..20e3f4a9c1
--- /dev/null
+++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
+4B 34 45 36 45 33 30 34 45 42 2D 45 47 43 46 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file
diff --git a/src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
new file mode 100644
index 0000000000..6d06e6297e
--- /dev/null
+++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
+4B 34 45 38 45 33 32 34 45 42 2D 45 47 43 46 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file
diff --git a/src/mainboard/google/glados/variants/lars/Makefile.inc b/src/mainboard/google/glados/variants/lars/Makefile.inc
new file mode 100644
index 0000000000..5ee7410572
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/Makefile.inc
@@ -0,0 +1,51 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += variant.c
+ramstage-y += variant.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0000 Single Channel 2GB
+SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0001 Dual Channel 8GB
+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0010 Dual Channel 4GB
+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0011 Single Channel 2GB
+SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0100 Single Channel 4GB
+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b0101 Dual Channel 8GB
+SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0110 Dual Channel 4GB
+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b0111 Single Channel 4GB
+SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b1000 Dual Channel 4GB
+SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1001 Dual Channel 8GB
+SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR # 0b1010 Dual Channel 4GB
+SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1011 Single Channel 4GB
+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b1100 Single Channel 4GB
+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b1101 Dual Channel 8GB
+SPD_SOURCES += empty # 0b1110
+SPD_SOURCES += empty # 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/glados/variants/lars/board_info.txt b/src/mainboard/google/glados/variants/lars/board_info.txt
new file mode 100644
index 0000000000..5b5e0bf047
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Lars (Acer Chromebook 14 for Work)
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/glados/variants/lars/data.vbt b/src/mainboard/google/glados/variants/lars/data.vbt
new file mode 100644
index 0000000000..0aac82c3b1
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/data.vbt
Binary files differ
diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb
new file mode 100644
index 0000000000..2eda59b0cd
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -0,0 +1,286 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # FSP Configuration
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "4" # 4s
+ register "PmConfigSlpSusMinAssert" = "3" # 4s
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_RING]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ # Enable Root port 1.
+ register "PcieRpEnable[0]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[0]" = "1"
+ # RP 1 uses SRCCLKREQ1#
+ register "PcieRpClkReqNumber[0]" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card)
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # SD
+ register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
+
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+ }"
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ device i2c 10 on end
+ end
+ end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "wake" = "GPE0_DW0_05"
+ device i2c 15 on end
+ end
+ end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on
+ chip drivers/i2c/nau8825
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
+ register "jkdet_enable" = "1"
+ register "jkdet_pull_enable" = "1"
+ register "jkdet_pull_up" = "1"
+ register "jkdet_polarity" = "1" # ActiveLow
+ register "vref_impedance" = "2" # 125kOhm
+ register "micbias_voltage" = "6" # 2.754
+ register "sar_threshold_num" = "4"
+ register "sar_threshold[0]" = "0x08"
+ register "sar_threshold[1]" = "0x12"
+ register "sar_threshold[2]" = "0x26"
+ register "sar_threshold[3]" = "0x73"
+ register "sar_hysteresis" = "0"
+ register "sar_voltage" = "6"
+ register "sar_compare_time" = "1" # 1us
+ register "sar_sampling_time" = "1" # 4us
+ register "short_key_debounce" = "3" # 30ms
+ register "jack_insert_debounce" = "7" # 512ms
+ register "jack_eject_debounce" = "0"
+ device i2c 1a on end
+ end
+ end # I2C #4
+ device pci 1c.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW0_16"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..1f464c5074
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 94
+#define DPTF_CPU_CRITICAL 99
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 70
+
+#define DPTF_TSR0_SENSOR_ID 2
+#define DPTF_TSR0_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR0_PASSIVE 65
+#define DPTF_TSR0_CRITICAL 70
+#define DPTF_TSR0_ACTIVE_AC0 60
+#define DPTF_TSR0_ACTIVE_AC1 48
+#define DPTF_TSR0_ACTIVE_AC2 42
+#define DPTF_TSR0_ACTIVE_AC3 39
+#define DPTF_TSR0_ACTIVE_AC4 36
+#define DPTF_TSR0_ACTIVE_AC5 34
+#define DPTF_TSR0_ACTIVE_AC6 32
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 65
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 0
+#define DPTF_TSR2_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR2_PASSIVE 65
+#define DPTF_TSR2_CRITICAL 70
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+ 0, // Revision
+ /*
+ * TODO : Need to update this Table after characterization.
+ * These are initial reference values.
+ */
+ /* Control, Trip Point, Speed, NoiseLevel, Power */
+ Package () {100, 0xFFFFFFFF, 4986, 220, 2200},
+ Package () {90, 0xFFFFFFFF, 4804, 180, 1800},
+ Package () {80, 0xFFFFFFFF, 4512, 145, 1450},
+ Package () {70, 0xFFFFFFFF, 4204, 115, 1150},
+ Package () {60, 0xFFFFFFFF, 3838, 90, 900},
+ Package () {50, 0xFFFFFFFF, 3402, 65, 650},
+ Package () {40, 0xFFFFFFFF, 2904, 45, 450},
+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},
+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},
+ Package () {10, 0xFFFFFFFF, 800, 10, 100},
+ Package () {0, 0xFFFFFFFF, 0, 0, 50}
+})
+
+Name (DART, Package () {
+ /* Fan effect on CPU */
+ 0, // Revision
+ Package () {
+ /*
+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+ * AC7, AC8, AC9
+ */
+ \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 0, 0, 0, 0, 0,
+ 0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 90, 75, 62, 55, 47,
+ 41, 0, 0, 0
+ }
+})
+#endif
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 25000, /* PowerLimitMinimum */
+ 25000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl
diff --git a/src/mainboard/google/glados/variants/lars/include/variant/ec.h b/src/mainboard/google/glados/variants/lars/include/variant/ec.h
new file mode 100644
index 0000000000..3c094b5cc6
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/include/variant/ec.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h
new file mode 100644
index 0000000000..a05c7022d8
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h
@@ -0,0 +1,234 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* MAX98357A SD_MODE */
+#define GPIO_SPEAKER_MAXIM_AMP_SDMODE GPP_B2
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_C6
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C13
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_C15
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_WLAN_WAKE GPE0_DW0_16
+
+/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
+
+/* Input device interrupt configuration */
+#define TOUCHPAD_INT_L GPP_B3_IRQ
+#define TOUCHSCREEN_INT_L GPP_E7_IRQ
+#define MIC_INT_L GPP_F10_IRQ
+
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
+#define EC_SCI_GPI GPE0_DW2_16
+#define EC_SMI_GPI GPP_E15
+
+#ifndef __ACPI__
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* PIRQA# */ PAD_CFG_NC(GPP_A7),
+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10),
+/* EC_HID_INT */ PAD_CFG_NC(GPP_A11),
+/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),
+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),
+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
+/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17),
+/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18),
+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
+/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),
+/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21),
+/* GYRO_INT */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
+/* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP),
+/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
+/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),
+/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
+/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* KEPLR_CLK_REQ */ PAD_CFG_NC(GPP_B7),
+/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),
+/* SSD_CLK_REQ */ PAD_CFG_NC(GPP_B9),
+/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* PCH_BUZZER */ PAD_CFG_GPO(GPP_B14, 0, DEEP),
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
+/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
+/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
+/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19),
+/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20),
+/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21),
+/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22),
+/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
+/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),
+/* SML0DATA */ PAD_CFG_NC(GPP_C4),
+/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
+/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),
+/* USB_CTL */ PAD_CFG_NC(GPP_C7),
+/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
+/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
+/* NFC_RST* */ PAD_CFG_NC(GPP_C10),
+/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11),
+/* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
+/* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
+/* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
+/* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0),
+/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1),
+/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2),
+/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3),
+/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4),
+/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),
+/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),
+/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),
+/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP),
+/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP),
+/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12),
+/* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21),
+/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22),
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
+/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),
+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
+/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),
+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
+/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
+/* SATALED# */ PAD_CFG_NC(GPP_E8),
+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
+/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
+/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
+/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),
+/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
+/* SD_CMD */ PAD_CFG_NC(GPP_G0),
+/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),
+/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),
+/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),
+/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),
+/* SD_CD# */ PAD_CFG_NC(GPP_G5),
+/* SD_CLK */ PAD_CFG_NC(GPP_G6),
+/* SD_WP */ PAD_CFG_NC(GPP_G7),
+/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+/* GPD7 */ PAD_CFG_NC(GPD7),
+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9),
+/* PM_SLP_S5# */ PAD_CFG_NC(GPD10),
+/* LANPHYC */ PAD_CFG_NC(GPD11),
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c
new file mode 100644
index 0000000000..297b149b4b
--- /dev/null
+++ b/src/mainboard/google/glados/variants/lars/variant.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <baseboard/variant.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+#define K4E6E304EB_MEM_ID 0x5
+
+#define MEM_SINGLE_CHAN0 0x0
+#define MEM_SINGLE_CHAN3 0x3
+#define MEM_SINGLE_CHAN4 0x4
+#define MEM_SINGLE_CHAN7 0x7
+#define MEM_SINGLE_CHANB 0xb
+#define MEM_SINGLE_CHANC 0xc
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 6, 5, 4, 7 },
+ { 2, 3, 0, 1, 6, 7, 4, 5 } };
+
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 200, 81, 162 };
+
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
+
+ /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EB -EGCF*/
+ const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 };
+
+ /* Default Rcomp Target assignment */
+ const u16 *targeted_rcomp = RcompTarget;
+
+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+ memcpy(pei_data->RcompResistor, RcompResistor,
+ sizeof(RcompResistor));
+
+ /* Override Rcomp Target assignment for specific SKU(s) */
+ if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID)
+ targeted_rcomp = StrengthendRcompTarget;
+
+ memcpy(pei_data->RcompTarget, targeted_rcomp,
+ sizeof(pei_data->RcompTarget));
+}
+
+int is_dual_channel(const int spd_index)
+{
+ return (spd_index != MEM_SINGLE_CHAN0
+ && spd_index != MEM_SINGLE_CHAN3
+ && spd_index != MEM_SINGLE_CHAN4
+ && spd_index != MEM_SINGLE_CHAN7
+ && spd_index != MEM_SINGLE_CHANB
+ && spd_index != MEM_SINGLE_CHANC);
+}