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authorJulius Werner <jwerner@chromium.org>2017-07-14 14:30:29 -0700
committerJulius Werner <jwerner@chromium.org>2017-07-19 18:15:15 +0000
commit6486e7819ccf4acf923d934d4293861f394cc065 (patch)
tree5b90d178a021829b9e268b9229b5e9e843668b32 /src/mainboard/google/gru/bootblock.c
parent4ed8b305539f661895d9fa950bb32fc653e37f47 (diff)
downloadcoreboot-6486e7819ccf4acf923d934d4293861f394cc065.tar.xz
google/gru: Add support for Scarlet rev1
This patch adds the necessary changes to support Scarlet revision 1. Since the differences to revision 0 are so deep, we have decided not to continue support for it in the same image. Therefore, this patch will break Scarlet rev0. All the deviations from other Gru boards are currently guarded by CONFIG_BOARD_GOOGLE_SCARLET. This should be changed later if we introduce more variants based on the newer Scarlet board design. Change-Id: I7a7cc11d9387ac1d856663326e35cfa5371e0af2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
Diffstat (limited to 'src/mainboard/google/gru/bootblock.c')
-rw-r--r--src/mainboard/google/gru/bootblock.c31
1 files changed, 19 insertions, 12 deletions
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 4320fcedad..7359f2a302 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -44,12 +44,12 @@ void bootblock_mainboard_early_init(void)
*/
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 0));
- /*
- * Let's enable these power rails here, we are already running the SPI
- * Flash based code.
- */
- gpio_output(GPIO(0, B, 2), 1); /* PP1500_EN */
- gpio_output(GPIO(0, B, 4), 1); /* PP3000_EN */
+ if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) {
+ /* Enable rails powering GPIO blocks, among other things.
+ These are EC-controlled on Scarlet and already on. */
+ gpio_output(GPIO_P15V_EN, 1);
+ gpio_output(GPIO_P30V_EN, 1);
+ }
#if IS_ENABLED(CONFIG_DRIVERS_UART)
_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
@@ -92,14 +92,21 @@ static void configure_ec(void)
static void configure_tpm(void)
{
if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) {
- gpio_input(GPIO(3, A, 4)); /* SPI0_MISO remove pull-up */
- gpio_input(GPIO(3, A, 5)); /* SPI0_MOSI remove pull-up */
- gpio_input(GPIO(3, A, 6)); /* SPI0_CLK remove pull-up */
- gpio_input_pullup(GPIO(3, A, 7)); /* SPI0_CS confirm */
-
rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
- write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
+ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) {
+ gpio_input(GPIO(2, B, 1)); /* SPI2_MISO no-pull */
+ gpio_input(GPIO(2, B, 2)); /* SPI2_MOSI no-pull */
+ gpio_input(GPIO(2, B, 3)); /* SPI2_CLK no-pull */
+ gpio_input_pullup(GPIO(2, B, 4)); /* SPI2_CS */
+ write32(&rk3399_grf->iomux_spi2, IOMUX_SPI2);
+ } else {
+ gpio_input(GPIO(3, A, 4)); /* SPI0_MISO no-pull */
+ gpio_input(GPIO(3, A, 5)); /* SPI0_MOSI no-pull */
+ gpio_input(GPIO(3, A, 6)); /* SPI0_CLK no-pull */
+ gpio_input_pullup(GPIO(3, A, 7)); /* SPI0_CS */
+ write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
+ }
gpio_input_irq(GPIO_TPM_IRQ, IRQ_TYPE_EDGE_RISING);
} else {