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| author | Shunqian Zheng <zhengsq@rock-chips.com> | 2016-08-10 04:45:50 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-16 21:19:00 +0200 |
| commit | 5fa08f3c0f34fec0fa3bf0a34425c96932d62931 (patch) | |
| tree | ac5c1d33f12a4235da841df55c563d3f216219bf /src/mainboard/google/gru | |
| parent | e4cc4733ebd4c6fc77de5f0a9963e9a938e57e5d (diff) | |
| download | coreboot-5fa08f3c0f34fec0fa3bf0a34425c96932d62931.tar.xz | |
Revert "rockchip: rk3399: enable sdhci clk for emmc"
This reverts commit 462e1413 ("rockchip: rk3399: enable sdhci clk
for emmc")
Enabling this clock in coreboot is no longer needed as it's handled
in the kernel driver now.
BUG=chrome-os-partner:52873
TEST=boot from usb/sdcard and check there is /dev/mmcblk0
BRANCH=none
Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0
Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/367421
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16152
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/gru')
| -rw-r--r-- | src/mainboard/google/gru/mainboard.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index e2205e0e0f..8a6cda203d 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -22,7 +22,6 @@ #include <soc/bl31_plat_params.h> #include <soc/clock.h> #include <soc/display.h> -#include <soc/emmc.h> #include <soc/grf.h> #include <soc/i2c.h> #include <soc/usb.h> @@ -42,8 +41,6 @@ static void configure_emmc(void) write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0)); rkclk_configure_emmc(); - - enable_emmc_clk(); } static void register_reset_to_bl31(void) |