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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-12-18 16:09:27 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-21 04:42:33 +0000 |
| commit | 6d8e0cdeabf0b0a128d9863a6f190facc73f4880 (patch) | |
| tree | 1d84b73b4a0e1a6852ca4f3f964bfe37aaed52dd /src/mainboard/google/hatch/Kconfig | |
| parent | 368598198d5c741d64b38d358e84c1694f97f486 (diff) | |
| download | coreboot-6d8e0cdeabf0b0a128d9863a6f190facc73f4880.tar.xz | |
mb/google/hatch: Enable H1 TPM support over SPI interface
Add code support to enable H1 TPM interfaced to SOC on GSPI0.
The TPM interrupt is mapped to GPP_C21.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30210
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/Kconfig')
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 7acfd09ce1..1c0208ff68 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -10,14 +10,13 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COFFEELAKE select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP - select TPM2 if BOARD_GOOGLE_BASEBOARD_HATCH @@ -29,6 +28,10 @@ config CHROMEOS select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + config DIMM_MAX int default 2 @@ -37,6 +40,9 @@ config DIMM_SPD_SIZE int default 512 +config DRIVER_TPM_SPI_BUS + default 0x1 + config GBB_HWID string depends on CHROMEOS @@ -62,17 +68,17 @@ config MAX_CPUS int default 8 -config VARIANT_DIR +config OVERRIDE_DEVICETREE string - default "hatch" if BOARD_GOOGLE_HATCH + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH -config DEVICETREE - string - default "variants/baseboard/devicetree.cb" +config TPM_TIS_ACPI_INTERRUPT + int + default 53 # GPE0_DW1_21 (GPP_C21) -config OVERRIDE_DEVICETREE +config VARIANT_DIR string - default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH + default "hatch" if BOARD_GOOGLE_HATCH config VBOOT select HAS_RECOVERY_MRC_CACHE |