diff options
| author | Shelley Chen <shchen@google.com> | 2018-12-18 13:11:25 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-22 12:14:20 +0000 |
| commit | 6bb563f29c5620746411e4766ac03113ec8b8280 (patch) | |
| tree | 45ff7e8cbe185ecb123145a92afee51a78b43eb3 /src/mainboard/google/hatch/chromeos.c | |
| parent | 74e0390e7487fc531d95cffe7736ab8b5512062a (diff) | |
| download | coreboot-6bb563f29c5620746411e4766ac03113ec8b8280.tar.xz | |
mb/google/hatch: Fixes to initial hatch mainboard checkin
Incorporating some feedback to initial hatch mainboard checking
(CL:30169) that came in after the CL merged.
Updated the chromeos.fmd with the following,
* SI_ALL = 3MB
* SI_BIOS = 16MB
BUG=b:20914069
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v
Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30296
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/chromeos.c')
| -rw-r--r-- | src/mainboard/google/hatch/chromeos.c | 37 |
1 files changed, 4 insertions, 33 deletions
diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 36fba45ac7..fa54148ee8 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -29,29 +29,15 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {-1, ACTIVE_HIGH, 0, "EC in RW"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; - - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; + return gpio_get(GPIO_PCH_WP); } void mainboard_chromeos_acpi_generate(void) @@ -63,18 +49,3 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } - -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - -int get_recovery_mode_switch(void) -{ - return cros_get_gpio_value(CROS_GPIO_REC); -} - -int get_lid_switch(void) -{ - return 1; -} |