diff options
| author | Shelley Chen <shchen@google.com> | 2018-12-18 13:11:25 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-22 12:14:20 +0000 |
| commit | 6bb563f29c5620746411e4766ac03113ec8b8280 (patch) | |
| tree | 45ff7e8cbe185ecb123145a92afee51a78b43eb3 /src/mainboard/google/hatch/chromeos.fmd | |
| parent | 74e0390e7487fc531d95cffe7736ab8b5512062a (diff) | |
| download | coreboot-6bb563f29c5620746411e4766ac03113ec8b8280.tar.xz | |
mb/google/hatch: Fixes to initial hatch mainboard checkin
Incorporating some feedback to initial hatch mainboard checking
(CL:30169) that came in after the CL merged.
Updated the chromeos.fmd with the following,
* SI_ALL = 3MB
* SI_BIOS = 16MB
BUG=b:20914069
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v
Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30296
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/hatch/chromeos.fmd | 30 |
1 files changed, 13 insertions, 17 deletions
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 663176978f..066cfbf62d 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -1,22 +1,20 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1000000 { + SI_ALL@0x0 0x300000 { SI_DESC@0x0 0x1000 - SI_EC@0x1000 0x100000 - SI_GBE@0x101000 0x2000 - SI_ME@0x103000 0xefd000 + SI_ME@0x1000 0x2ff000 } SI_BIOS@0x1000000 0x1000000 { - RW_SECTION_A@0x0 0x280000 { + RW_SECTION_A@0x0 0x300000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x26ffc0 - RW_FWID_A@0x27ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x2effc0 + RW_FWID_A@0x2fffc0 0x40 } - RW_SECTION_B@0x280000 0x280000 { + RW_SECTION_B@0x300000 0x300000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x26ffc0 - RW_FWID_B@0x27ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x2effc0 + RW_FWID_B@0x2fffc0 0x40 } - RW_MISC@0x500000 0x30000 { + RW_MISC@0x600000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -29,17 +27,15 @@ FLASH@0xfe000000 0x2000000 { RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - CONSOLE@0x530000 0x20000 - RW_LEGACY(CBFS)@0x550000 0x6b0000 - WP_RO@0xc00000 0x400000 { + RW_LEGACY(CBFS)@0x630000 0x5a0000 + WP_RO@0xbd0000 0x430000 { RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x3f0000 { + RO_SECTION@0x4000 0x42c000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x300000 + COREBOOT(CBFS)@0xf0000 0x33c000 } } } |