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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-12-13 18:08:51 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:54:24 +0000 |
| commit | f107b6c3a0beff0eea343d051dc460e033acd04c (patch) | |
| tree | 7ad9150293491f584ac4f379d36a7b010a00c7fa /src/mainboard/google/hatch/dsdt.asl | |
| parent | d4f39abebf069517321b5fc6157ad65318b13cf3 (diff) | |
| download | coreboot-f107b6c3a0beff0eea343d051dc460e033acd04c.tar.xz | |
mb/google/hatch: Clean up duplicate method
Moving Enable/disable GPIO clock gating to soc level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/hatch/dsdt.asl | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1e7f760a7b..8807191fcb 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -40,9 +40,6 @@ DefinitionBlock( #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } - - /* Mainboard hooks */ - #include "mainboard.asl" } #if CONFIG(CHROMEOS) |