diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2019-02-21 15:18:54 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-27 11:04:29 +0000 |
| commit | 51749b276644f6e74c0f9e90647a0f752ac627d3 (patch) | |
| tree | 5d44029d17d423d2214aaeee37b2535d1b9cd299 /src/mainboard/google/hatch/variants/baseboard/devicetree.cb | |
| parent | ce529b631819574c3e1f6b10e60725df1638013e (diff) | |
| download | coreboot-51749b276644f6e74c0f9e90647a0f752ac627d3.tar.xz | |
mb/google/hatch: update SD card detect GPIO
SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO,
expose that GPIO for kernel to configure card detect IRQ.
BUG=b:123350329
Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f913e77558..e2c3392eef 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -89,7 +89,7 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[1]" = "1" # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" + register "sdcard_cd_gpio" = "vSD3_CD_B" # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" |