diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2018-12-16 13:10:58 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-23 05:12:14 +0000 |
commit | 4b85d46170ef44ab88b9cf844e3d3feaf9e7e89e (patch) | |
tree | 23405bc1cbb8224ed4043e5a90a837b4966ea633 /src/mainboard/google/hatch/variants/baseboard/memory.c | |
parent | 09e7b998379225fb0b79e5fd2fb5ba9b95bd6961 (diff) | |
download | coreboot-4b85d46170ef44ab88b9cf844e3d3feaf9e7e89e.tar.xz |
mb/google/hatch: Add memory init setup for hatch
This implementation adds below support:
1. Add support to read memory strap.
2. Add support to configure below memory parameters
-> rcomp resistor configuration
-> dqs mapping
-> ect and ca vref config
3. Include SPD configuration
BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot
Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30248
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard/memory.c')
-rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/memory.c | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c new file mode 100644 index 0000000000..80f3ba4260 --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> +#include <soc/cnl_memcfg_init.h> + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 120, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 120, 81, 100 }, + + /* Baseboard Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, +}; + +const struct cnl_mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} |