diff options
author | Wisley Chen <wisley.chen@quantatw.com> | 2019-12-19 18:08:09 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:45:26 +0000 |
commit | a8a7374e843bae6c98ad242d2870bef6043d165d (patch) | |
tree | c130f01788a4d07c7cb8aec588383b2570ec37a2 /src/mainboard/google/hatch/variants/jinlon/gpio.c | |
parent | e15087691064157532410050c87f6a27f9b85353 (diff) | |
download | coreboot-a8a7374e843bae6c98ad242d2870bef6043d165d.tar.xz |
hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon
In https://review.coreboot.org/c/coreboot/+/37459
(commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset
pin control of FPMCU to var/board/ramstage, but does not implement it for
dratini/jinlon. So, add it in dratini/jinlon.
BUG=b:146366921
TEST=emerge-hatch coreboot
Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/jinlon/gpio.c')
-rw-r--r-- | src/mainboard/google/hatch/variants/jinlon/gpio.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 12d96d8496..2bf97b1046 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -110,3 +110,32 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} |