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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-07-09 13:33:04 -0600
committerMartin Roth <martinroth@google.com>2019-07-11 15:01:41 +0000
commit145748bf25b658da1d2951201413ba9b0c68a266 (patch)
tree53e509a8d326382445e36236b2850e1d71bf2c12 /src/mainboard/google/hatch/variants
parent20cfc87ca07ce1ac07c47480e1a6a5bc0a1e1090 (diff)
downloadcoreboot-145748bf25b658da1d2951201413ba9b0c68a266.tar.xz
mb/google/hatch: Disable GPIO community dynamic clock gating
The dynamic clock gating is causing boards to miss interrupts whose pulses are shorter than 4us. Disable it using FSP UPDs. BUG=b:130764684 BRANCH=none TEST=Compiles Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 9a9125396c..a4700321a4 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -95,12 +95,12 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- # Disable clock gating on this community so that cr50's short irq
- # pulses won't be missed.
+ # Disable dynamic clock gating; with bits 0-5 set in these registers,
+ # some short interrupt pulses were missed (esp. cr50 irq)
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on