diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2020-06-12 12:17:33 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-14 03:43:44 +0000 |
| commit | 0490f5affb024005850340f6be69a390961120cc (patch) | |
| tree | 6f9eca5ff4b45a3789b5b8a26e544ac91366f7f9 /src/mainboard/google/hatch/variants | |
| parent | ad78553f5d2456f1a7c22f9e9694b8c3c7e30693 (diff) | |
| download | coreboot-0490f5affb024005850340f6be69a390961120cc.tar.xz | |
mb/google/hatch: Switch USB2 port1 and port3 on Noibat
Switch USB2 port1 and port3 for noibat due to circuit change.
BUG=b:154585046,b:156429564
BRANCH=none
TEST=none
Change-Id: I711038624f3efe397be73c29a940b3e17802598f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants')
| -rw-r--r-- | src/mainboard/google/hatch/variants/noibat/overridetree.cb | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index 050a75a4cc..ed5fab2794 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -21,9 +21,6 @@ chip soc/intel/cannonlake }" # USB configuration - # NOTE: This only applies to Puff, - # usb2_ports[1] and usb2_ports[3] were swapped on - # reference schematics after Puff has been built. register "usb2_ports[0]" = "{ .enable = 1, .ocpin = OC2, @@ -32,23 +29,23 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 2 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[2]" = "{ + register "usb2_ports[1]" = "{ .enable = 1, - .ocpin = OC3, + .ocpin = OC1, .tx_bias = USB2_BIAS_0MV, .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "{ + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ .enable = 1, - .ocpin = OC1, + .ocpin = OC3, .tx_bias = USB2_BIAS_0MV, .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "{ .enable = 1, @@ -125,7 +122,7 @@ chip soc/intel/cannonlake # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as noibat variant does not have them. register "PchHdaAudioLinkSsp1" = "0" register "PchHdaAudioLinkDmic0" = "0" |