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| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2019-02-20 15:05:33 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-21 16:22:54 +0000 |
| commit | caa85f249d5f8be09ecd7b03e9e87a2fac0190dc (patch) | |
| tree | edd5f7473b1ab799fbd47396d4ab7fdd5fd19ce2 /src/mainboard/google/hatch | |
| parent | 00bb441ba4f9d427901043db0bb686d389e3adca (diff) | |
| download | coreboot-caa85f249d5f8be09ecd7b03e9e87a2fac0190dc.tar.xz | |
soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all
DDI ports are enabled and hence configures the HPD and CLK for DDI ports.
This patch initializes only the required UPDs to enable display ports.
BUG=b:123907904
TEST=DP devices working correctly.
Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 16a0ef134f..0299ded7b5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -66,6 +66,11 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "44" register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 |