diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2018-12-26 19:02:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-28 06:45:21 +0000 |
| commit | 3736127c979f52975bbad135548a36fd7585e7fd (patch) | |
| tree | 0a8e13bfd48060718b9718ed6d71ccb25d785526 /src/mainboard/google/hatch | |
| parent | 3c0c3619bcd0c6d25bdf5492be6ba8bb2d5bb410 (diff) | |
| download | coreboot-3736127c979f52975bbad135548a36fd7585e7fd.tar.xz | |
mb/google/hatch: Enable SPI controller for Hatch
Enable SPI controller(D31:F5).
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: I4d3acd3f31650d5b39927f8e3cfbb6187541653f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0b3f469b77..a996a703b2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -101,7 +101,7 @@ chip soc/intel/cannonlake device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI + device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE end end |