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authorRonald G. Minnich <rminnich@gmail.com>2018-12-19 17:52:43 -0800
committerron minnich <rminnich@gmail.com>2019-01-17 04:59:09 +0000
commit05358047290b5e60cf3c0dc7e967267a03d5c4ce (patch)
treeed4340b82c8fa9ae78bf7b8095aa1ad952ef8202 /src/mainboard/google/hatch
parentcc394d4d37533a4977c1da629c8ebf405a91d32a (diff)
downloadcoreboot-05358047290b5e60cf3c0dc7e967267a03d5c4ce.tar.xz
riscv: create Kconfig architecture features for new parts
RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/30348 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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