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authorHung-Te Lin <hungte@chromium.org>2019-03-04 16:48:05 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-05 20:52:06 +0000
commite5861828ee4357a3df94a8670da1fe9e628deb47 (patch)
treed1d6fe40fad95ff285c44ef2171626f3833d4450 /src/mainboard/google/hatch
parent49a44505637ecfa3a6c1606bc0986e70397966b0 (diff)
downloadcoreboot-e5861828ee4357a3df94a8670da1fe9e628deb47.tar.xz
mainboard: Enable PRESERVE flag in all vboot/chromeos FMD files
For Chrome OS (or vboot), The PRESERVE flags should be applied on following sections: RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE, RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768), SI_PDR (chromium:936768) With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in the future. But it's still no harm to use it if there are multiple sections all needing to be preserved. BUG=chromium:936768 TEST=Builds google/eve and google/kukui inside Chrome OS source tree. Also boots successfully on eve and kukui devices. Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/hatch')
-rw-r--r--src/mainboard/google/hatch/chromeos.fmd8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd
index e0007937d3..393ac808b5 100644
--- a/src/mainboard/google/hatch/chromeos.fmd
+++ b/src/mainboard/google/hatch/chromeos.fmd
@@ -23,18 +23,18 @@ FLASH@0xfe000000 0x2000000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x20000
}
- RW_ELOG@0x30000 0x4000
+ RW_ELOG(PRESERVE)@0x30000 0x4000
RW_SHARED@0x34000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
- RW_VPD@0x38000 0x2000
- RW_NVRAM@0x3a000 0x6000
+ RW_VPD(PRESERVE)@0x38000 0x2000
+ RW_NVRAM(PRESERVE)@0x3a000 0x6000
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO@0x1800000 0x400000 {
- RO_VPD@0x0 0x4000
+ RO_VPD(PRESERVE)@0x0 0x4000
RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40