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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-12-24 18:24:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-25 03:42:59 +0000 |
| commit | 6aaae1c89341f6f25b003fa0976cdc0620a75d34 (patch) | |
| tree | edcc1881441f70aff7900fbdca4c76ca9fe2bc71 /src/mainboard/google/hatch | |
| parent | 0dfda74408097be2c04f9999011b8fa3f43fc7cf (diff) | |
| download | coreboot-6aaae1c89341f6f25b003fa0976cdc0620a75d34.tar.xz | |
mb/google/hatch: Enable EC LPC interface and configure IO decode range
Enable EC LPC interface and configure below LPC IO decode ranges:
1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b6dec1381e..6b4e45f91b 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2e171b0579..3cdc3e01a1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -10,6 +10,12 @@ chip soc/intel/cannonlake register "gpe0_dw1" = "PMC_GPP_C" register "gpe0_dw2" = "PMC_GPP_D" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |