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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-06-18 10:36:40 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-22 22:57:13 +0000 |
| commit | 6e5e24e2b307ec18a0eb36f2141349dcf0304907 (patch) | |
| tree | dd4f6ba288f67d4e9f09d3babd47958a15accf00 /src/mainboard/google/hatch | |
| parent | 03743b7fa3217f13f019bce9b8680c5936375d71 (diff) | |
| download | coreboot-6e5e24e2b307ec18a0eb36f2141349dcf0304907.tar.xz | |
cbmem: Remove IDs for TSEG and BERT
Remove the changes added in
commit 80df052d3 "cbmem: Add IDs for TSEG and BERT table data"
No platform uses either ID. TSEG in cbmem is incompatible with stage
cache. BERT reserved data in cbmem is unusable in Linux.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42532
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch')
0 files changed, 0 insertions, 0 deletions