diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2019-12-23 23:12:19 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2019-12-23 22:09:08 +0000 |
| commit | e8b7ff1ab51be3fd8a98a3fc1dfdf15aa800cab5 (patch) | |
| tree | 29247221b13cd5a3faa7cc5d5cf480deee45680d /src/mainboard/google/hatch | |
| parent | 95bff2e17e8b9e84e588aeb9504e086174edd0b0 (diff) | |
| download | coreboot-e8b7ff1ab51be3fd8a98a3fc1dfdf15aa800cab5.tar.xz | |
mainboard/google/puff: Enable func0 of 1c for nic
Two things here:
i. ) FSP requires that function 0 be enabled whenever any non-zero
functions hang under the same bus:device.
ii.) FSP reorders function 6 RP to be function 0 if function 0 is
indeed unused.
BUG=b:146437819
BRANCH=none
TEST=none
Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/variants/puff/overridetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index a24d7fc80a..b99c1f240a 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -175,7 +175,8 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on end # PCI Express Port 7, RTL8111H Ethernet NIC. + device pci 1c.0 on end # FSP requires func0 be enabled. + device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). device pci 1e.3 off end # GSPI #1 end |