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authorSubrata Banik <subrata.banik@intel.com>2019-10-30 16:48:19 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-11-01 11:50:03 +0000
commit2715cdb3f32fcebdd1de6870a665a2b613c07e60 (patch)
tree5addc7091dfc055927c7edbbb44f36a45114e77c /src/mainboard/google/hatch
parent1e8f305957c98cb224574e1fa81938c9a692bd48 (diff)
downloadcoreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.tar.xz
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch')
-rw-r--r--src/mainboard/google/hatch/dsdt.asl6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index e2959a788a..9329b58a79 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -52,10 +52,10 @@ DefinitionBlock(
#endif
/* Chipset specific sleep states */
- #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Low power idle table */
- #include <soc/intel/cannonlake/acpi/lpit.asl>
+ /* Low power idle table */
+ #include <soc/intel/cannonlake/acpi/lpit.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)