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authorEdward O'Callaghan <quasisec@google.com>2020-07-02 12:50:26 +1000
committerEdward O'Callaghan <quasisec@chromium.org>2020-07-03 00:04:16 +0000
commit7b2f5030382ada910c0a4a7dd89af0447208e988 (patch)
tree147a2e02f3d3b8c4d5601cf53e22cd0585799992 /src/mainboard/google/hatch
parent8056c910bc49deebd925adc62c180e726b00bdcf (diff)
downloadcoreboot-7b2f5030382ada910c0a4a7dd89af0447208e988.tar.xz
mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Wyvern
V.2: Spare USB routed internally to another peripheral and so no plug event hook needed. BUG=b:1603699358,b:157479891 BRANCH=none TEST=none Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch')
-rw-r--r--src/mainboard/google/hatch/variants/wyvern/overridetree.cb10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
index 55ce5ea084..c394977f6e 100644
--- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
@@ -81,6 +81,16 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
+ # Bitmap for Wake Enable on USB attach/detach
+ register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(6)"
+ register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(5)"
+
# Enable eMMC HS400
register "ScsEmmcHs400Enabled" = "1"