diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2020-01-17 15:14:53 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-01-18 03:48:53 +0000 |
| commit | 6455740c0939ac24a1d6b5363cdd732f75dab299 (patch) | |
| tree | 7be93609e071394f9830e5a477e82dbb1f95e9ef /src/mainboard/google/hatch | |
| parent | 8d6eae5d6d601934bc85fc07040af0dd853058b8 (diff) | |
| download | coreboot-6455740c0939ac24a1d6b5363cdd732f75dab299.tar.xz | |
mainboard/puff: Fix ACPI tables to advertise correct features
Provide Puff with it's own copy of ec.h copied from the
baseboard/includes however with the battery, lid and ps2
defines stripped.
This is to ensure the correct ASL is generated so that we don't
advertise PS2 keyboard support and battery/lid interrupts which
don't exist.
V.2: drop EC_ENABLE_ALS_DEVICE as well.
V.3: set MAINBOARD_EC_SMI_EVENTS to 0 and drop
EC_HOST_EVENT_LID_CLOSED smi event.
V.4: drop EC_HOST_EVENT_MODE_CHANGE &&
provide wake pin for EC for _PRW WoL method
V.5: drop EC_HOST_EVENT_KEY_PRESSED
BUG=b:147850335
BRANCH=none
TEST=builds
Change-Id: If13bd124c7229ced996efb841980604d13be09af
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/variants/puff/include/variant/ec.h | 49 |
1 files changed, 47 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 768987d225..501fab0dde 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2018 Intel Corporation. * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify @@ -16,6 +17,50 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include <baseboard/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> -#endif +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS 0 + +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with power button */ +#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Provide wake pin for EC for _PRW WoL method */ +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* VARIANT_EC_H */ |