Combine Broadwell Chromeboxes using variant board scheme

Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.

Additional changes besides simple consolidation include:
 - simplify power LED functions
 - simplify HDA verb definitions using azelia macros
 - use common SoC functions to generate FADT table
 - correct FADT table header version
 - remove unused haswell_pci_irqs.asl
 - remove unused header includes (various)
 - set sane default fan speed (0x4d) for all variants

Variant setup modeled after google/beltino

Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 59 insertions, 0 deletions

diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c
new file mode 100644
index 0000000000..4eeabbeec4
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 0;
+
+	/* P0: VP8 */
+	pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0,
+			   USB_PORT_MINI_PCIE);
+	/* P1: Port A, CN22 */
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+			   USB_PORT_INTERNAL);
+	/* P2: Port B, CN23 */
+	pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
+			   USB_PORT_INTERNAL);
+	/* P3: WLAN */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P4: Port C, CN25 */
+	pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P5: Port D, CN25 */
+	pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P6: Card Reader */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: EMPTY */
+	pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0,
+			   USB_PORT_SKIP);
+
+	/* P1: CN22 */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: CN23 */
+	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+	/* P3: CN25 */
+	pei_data_usb3_port(pei_data, 2, 1, 2, 0);
+	/* P4: CN25 */
+	pei_data_usb3_port(pei_data, 3, 1, 2, 0);
+}