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authorMatt DeVillier <matt.devillier@gmail.com>2018-08-01 13:05:14 -0500
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-08-01 22:23:54 +0000
commit3044af7adc652f41670f8de0c3c54bc09f632079 (patch)
treef1b936af303292c7e3ed35a188809fbc3f9a249a /src/mainboard/google/jecht
parent9fe248fbeca2c62153dc4d8d89bfc9cd1d84dcd3 (diff)
downloadcoreboot-3044af7adc652f41670f8de0c3c54bc09f632079.tar.xz
mb/google,samsung/*: Add LPC TPM chip driver to devicetree
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27786 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/jecht')
-rw-r--r--src/mainboard/google/jecht/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index 8a2129f4eb..d34bf7a5d5 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -76,6 +76,9 @@ chip soc/intel/broadwell
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
chip superio/ite/it8772f
# Skip keyboard init
register "skip_keyboard" = "1"