summaryrefslogtreecommitdiff
path: root/src/mainboard/google/jecht
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-12-22 16:11:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-15 17:57:18 +0000
commit4d56a0625516ba436903d59d9c0a4a13827d89be (patch)
tree764641e18971d6e4e54a9e0142595dc3104da106 /src/mainboard/google/jecht
parent5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2 (diff)
downloadcoreboot-4d56a0625516ba436903d59d9c0a4a13827d89be.tar.xz
nb/intel/broadwell: Add an option for where verstage starts
Previously broadwell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. With a separate verstage the romstage becomes an RW stage. The mrc.bin however is only added to the RO COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I900233cadb3c76da329fb98f93917570e633365f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/jecht')
-rw-r--r--src/mainboard/google/jecht/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc
index 39e9b339e8..28a284e759 100644
--- a/src/mainboard/google/jecht/Makefile.inc
+++ b/src/mainboard/google/jecht/Makefile.inc
@@ -16,6 +16,7 @@
subdirs-y += spd
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += lan.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c