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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-11-17 14:34:52 -0700 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-12-19 21:51:31 +0000 |
| commit | 8f454fd2ea86edf2a0646d28a1451116c3de7a9a (patch) | |
| tree | 42fd14634efa8002288a3354758ceb99e4f42890 /src/mainboard/google/jecht | |
| parent | badd4602293835404036ad35528452a397648b5b (diff) | |
| download | coreboot-8f454fd2ea86edf2a0646d28a1451116c3de7a9a.tar.xz | |
soc/amd/picasso: Reduce romstage.c
Remove the old Stoney Ridge postcar stack frame setup. Reduce
romstage.c to basic functionality. Until AGESA's reporting of
memory configuration is available, use the TOM register as an
indicator for the top of usable memory.
Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/google/jecht')
0 files changed, 0 insertions, 0 deletions