chromeos mainboards: remove chromeos.asl

Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

4 files changed, 12 insertions, 20 deletions

diff --git a/src/mainboard/google/jecht/acpi/chromeos.asl b/src/mainboard/google/jecht/acpi/chromeos.asl
deleted file mode 100644
index 492ee6b272..0000000000
--- a/src/mainboard/google/jecht/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
-	Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index cc19666d15..c22f942960 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -94,3 +94,13 @@ void save_chromeos_gpios(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
 }
 #endif
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl
index b434727ec8..3132aab20a 100644
--- a/src/mainboard/google/jecht/dsdt.asl
+++ b/src/mainboard/google/jecht/dsdt.asl
@@ -47,7 +47,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states
diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c
index 58c0190b59..cb17797e97 100644
--- a/src/mainboard/google/jecht/mainboard.c
+++ b/src/mainboard/google/jecht/mainboard.c
@@ -30,6 +30,7 @@
 #include <arch/io.h>
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
 void mainboard_suspend_resume(void)
@@ -135,6 +136,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 #if CONFIG_VGA_ROM_RUN
 	/* Install custom int15 handler for VGA OPROM */
 	mainboard_interrupt_handlers(0x15, &int15_handler);