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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-23 19:08:01 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-25 16:03:37 +0000 |
| commit | 17887d08fee6d10bc4ff8758694b88435365e5d7 (patch) | |
| tree | 03ef6c6afe204dd47c26177974b0c7d6cc60f574 /src/mainboard/google/jecht | |
| parent | b14b55daafbd953d04a3bbf9a66bc7fc5ebd277f (diff) | |
| download | coreboot-17887d08fee6d10bc4ff8758694b88435365e5d7.tar.xz | |
mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__
Use explicit simple PCI config accessors here.
Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/jecht')
| -rw-r--r-- | src/mainboard/google/jecht/chromeos.c | 23 |
1 files changed, 4 insertions, 19 deletions
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 2b72cae036..f2db756e5e 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -28,9 +29,6 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 -#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -44,36 +42,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -85,7 +70,7 @@ void init_bootmode_straps(void) /* Developer: Virtual */ - pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { |